| /external/llvm/test/CodeGen/ARM/ |
| D | ifcvt3.ll | 3 ; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -check-prefix CHECK-V4-BX
29 ; CHECK-V4-BX: bx
30 ; CHECK-V4-BX: bx
31 ; CHECK-V4-BX-NOT: bx
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| D | none-macho-v4t.ll | 7 ; BX can only take a register before v5t came along, so we must materialise
|
| /external/llvm/test/MC/X86/ |
| D | intel-syntax.s | 379 shld DX, BX
380 shld DX, BX, CL
381 shld DX, BX, 1
382 shld [RAX], BX
383 shld [RAX], BX, CL
384 shrd DX, BX
385 shrd DX, BX, CL
386 shrd DX, BX, 1
387 shrd [RAX], BX
388 shrd [RAX], BX, CL
[all …]
|
| /external/libhevc/common/arm/ |
| D | ihevc_mem_fns.s | 130 BX LR
162 BX LR
200 BX LR
234 BX LR
273 BX LR
|
| /external/clang/test/Layout/ |
| D | ms-x86-primary-bases.cpp | 194 struct BX : B0X, B1X { int a; BX() : a(0xf000000B) {} virtual void g() { printf("B"); } }; in BX() argument
325 sizeof(BX)+
|
| D | ms-x86-aligned-tail-padding.cpp | 404 struct BX : B4X, virtual B2X, virtual B6X, virtual B3X { struct
406 BX() : a(0xf000000B) {} in BX() argument
532 sizeof(BX)+
|
| D | ms-x86-lazy-empty-nonvirtual-base.cpp | 661 struct BX : B2X, B1X, B3X, B4X, virtual B0X { struct
663 BX() : a(0x0000000B) { printf(" B = %p\n", this); } in BX() argument
832 sizeof(BX)+
|
| /external/OpenCSD/decoder/tests/snapshots/tc2-ptm-rstk-t32/ds-5_trace_dump/ |
| D | a15_rs.txt | 12 S:0x80001BB4 E12FFF1E BX lr
113 S:0x80000F84 4770 BX lr
127 S:0x80000F84 4770 BX lr
145 S:0x80000F84 4770 BX lr
164 S:0x80001BC0 4770 BX lr
177 S:0x80000F84 4770 BX lr
184 S:0x80001BC4 4770 BX lr
284 S:0x80000FB4 4770 BX lr
296 S:0x80000FB4 4770 BX lr
308 S:0x80000FB4 4770 BX lr
[all …]
|
| /external/llvm/lib/Target/PowerPC/ |
| D | p9-instrs.txt | 250 [PO BF // A B XO AX BX /] xscmpexpdp
255 [PO T A B XO AX BX TX] xscmpeqdp xscmpgedp xscmpgtdp xscmpnedp
258 [PO T A B Rc XO AX BX TX] xvcmpnedp xvcmpnedp. xvcmpnesp xvcmpnesp.
279 [PO T XO B XO BX TX] xscvdphp xscvhpdp
283 [PO T XO B XO BX TX] xvcvhpsp xvcvsphp
302 [PO T A B XO AX BX TX] xviexpdp xviexpsp
306 [PO T / UIM B XO BX TX] xxextractuw xxinsertw
309 [PO BF DCMX B XO BX /]
310 [PO T XO B XO BX /] xsxexpdp xsxsigdp
315 [PO T XO B XO BX TX] xvxexpdp xvxexpsp
[all …]
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 78 X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX, in initLLVMToSEHAndCVRegMapping()
299 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
311 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
348 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
349 return X86::BX; in getX86SubSuperRegisterOrZero()
384 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
420 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
|
| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_shiftrountine.s | 59 BX lr
104 BX lr
|
| D | ixheaacd_ffr_divide16.s | 49 BX lr
|
| D | ia_xheaacd_mps_mulshift.s | 45 BX LR
|
| D | ixheaacd_lap1.s | 49 BX lr
|
| D | ixheaacd_harm_idx_zerotwolp.s | 107 BX lr
|
| D | ixheaacd_expsubbandsamples.s | 112 BX lr
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonBitTracker.cpp | 692 uint16_t BX = im(2); in evaluate() local
693 RC[BX] = RC[BX].is(0) ? BT::BitValue::One in evaluate()
694 : RC[BX].is(1) ? BT::BitValue::Zero in evaluate()
701 uint16_t BX = im(2); in evaluate() local
704 RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero) in evaluate()
705 .fill(W1+(W1-BX), W0, Zero); in evaluate()
706 RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1); in evaluate()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBitTracker.cpp | 618 uint16_t BX = im(2); in evaluate() local
619 RC[BX] = RC[BX].is(0) ? BT::BitValue::One in evaluate()
620 : RC[BX].is(1) ? BT::BitValue::Zero in evaluate()
627 uint16_t BX = im(2); in evaluate() local
630 RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero) in evaluate()
631 .fill(W1+(W1-BX), W0, Zero); in evaluate()
632 RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1); in evaluate()
|
| /external/llvm/test/CodeGen/X86/ |
| D | optimize-max-3.ll | 48 ; CHECK-NEXT: incl [[BX:%[a-z0-9]+]]
49 ; CHECK-NEXT: cmpl [[R14:%[a-z0-9]+]], [[BX]]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 100 {codeview::RegisterId::BX, X86::BX}, in initLLVMToSEHAndCVRegMapping()
621 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
633 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
670 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
671 return X86::BX; in getX86SubSuperRegisterOrZero()
706 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
742 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
|
| /external/XNNPACK/src/f32-gemm/gen/ |
| D | 4x8-minmax-aarch32-neon-ld64.S | 162 BX lr
217 BX lr
|
| D | 4x8-minmax-aarch32-neon-cortex-a7.S | 182 BX lr
237 BX lr
|
| /external/XNNPACK/src/f32-gemm/ |
| D | 4x4-aarch32-vfp-ld64.S | 162 BX lr
218 BX lr
|
| /external/XNNPACK/src/u32-filterbank-accumulate/ |
| D | aarch32-arm-x1.S | 86 BX lr
|
| /external/arm-neon-tests/ |
| D | InitCache.s | 49 BX lr
|