Searched refs:Bridge (Results 1 – 25 of 78) sorted by relevance
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| /external/tcpdump/tests/ |
| D | lldp_cdp-ev.out | 50 System Capabilities [Bridge, Router] (0x0014)
51 Enabled Capabilities [Bridge] (0x0004)
72 System Capabilities [Bridge, Router] (0x0014)
73 Enabled Capabilities [Bridge] (0x0004)
94 System Capabilities [Bridge, Router] (0x0014)
95 Enabled Capabilities [Bridge] (0x0004)
116 System Capabilities [Bridge, Router] (0x0014)
117 Enabled Capabilities [Bridge] (0x0004)
176 System Capabilities [Bridge, Router] (0x0014)
177 Enabled Capabilities [Bridge] (0x0004)
[all …]
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| D | lldp_mudurl-v.out | 11 System Capabilities [Bridge, WLAN AP, Router, Station Only] (0x009c)
42 System Capabilities [Bridge, WLAN AP, Router, Station Only] (0x009c)
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| D | lldp-infinite-loop-2.out | 29 EVB Bridge Status
33 R: 7, RTE: 21, EVB Mode: EVB Bridge [1]
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| D | lldp_mudurl-vv.out | 22 System Capabilities [Bridge, WLAN AP, Router, Station Only] (0x009c)
75 System Capabilities [Bridge, WLAN AP, Router, Station Only] (0x009c)
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| D | evb.out | 50 EVB Bridge Status
54 R: 7, RTE: 20, EVB Mode: EVB Bridge [1]
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| /external/tensorflow/tensorflow/compiler/mlir/tensorflow/g3doc/ |
| D | enable_mlir_bridge.md | 1 # Enable MLIR-Based new TPU Bridge
3 **MLIR-Based new TPU Bridge is an experimental feature, tread lightly.**
8 Bridge is enabled or not. You can set it by using the following example code:
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| /external/python/bumble/docs/mkdocs/src/apps_and_tools/ |
| D | index.md | 11 …* [HCI Bridge](hci_bridge.md) - a HCI transport bridge to connect two HCI transports and filter/sn…
12 …* [Golden Gate Bridge](gg_bridge.md) - a bridge between GATT and UDP to use with the Golden Gate "…
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| /external/tensorflow/tensorflow/compiler/aot/ |
| D | BUILD | 177 mlir_components = "Bridge",
204 mlir_components = "Bridge",
231 mlir_components = "Bridge",
257 mlir_components = "Bridge",
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| /external/tensorflow/tensorflow/compiler/mlir/tf2xla/ |
| D | BUILD | 2 # TF2XLA Bridge and related components.
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| /external/ppp/pppd/plugins/radius/etc/ |
| D | dictionary.ascend | 62 ATTRIBUTE Ascend-Bridge-Address 168 string
124 ATTRIBUTE Ascend-Bridge 230 integer
188 VALUE Ascend-Bridge Bridge-No 0
189 VALUE Ascend-Bridge Bridge-Yes 1
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| /external/python/bumble/docs/mkdocs/src/use_cases/ |
| D | use_case_6.md | 12 | Device | Transport | Bridge | Transport | | | |
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| /external/llvm/lib/Target/X86/ |
| D | X86SchedSandyBridge.td | 1 //=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=//
10 // This file defines the machine model for Sandy Bridge to support instruction
34 // Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
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| D | X86.td | 750 // We currently use the Sandy Bridge model as the default scheduling model as
751 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
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| /external/tensorflow/tensorflow/compiler/aot/tests/ |
| D | test_error_message.lit.pbtxt | 1 # RUN: not tfcompile --graph=%s --config=%s.config.pbtxt --mlir_components=Bridge --debug_info=%s.d…
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| /external/igt-gpu-tools/man/ |
| D | intel_panel_fitter.rst | 34 Pipe to be used (A, B or C, but C is only present on Ivy Bridge and newer).
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| /external/mesa3d/docs/relnotes/ |
| D | 11.0.8.rst | 77 - Revert "i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge"
112 - i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge
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| D | 19.1.2.rst | 41 on Ivy Bridge
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| D | 17.1.2.rst | 113 - i965: Rework Sandy Bridge HiZ and stencil layouts
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| /external/python/bumble/docs/mkdocs/src/hardware/ |
| D | index.md | 6 …/tcp_server.md) or the [UDP Transport](../transports/udp.md)) to an [HCI Bridge](../apps_and_tools…
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| /external/cpu_features/ |
| D | README.md | 111 the most efficient (e.g. AVX on Sandy Bridge). We provide a function to retrieve
115 set—but only if it's not Sandy Bridge.
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86.td | 342 // Sandy Bridge and newer processors can use SHLD with the same source on both
350 // Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
366 // Sandy Bridge and newer processors have many instructions that can be
1228 // We currently use the Sandy Bridge model as the default scheduling model as
1229 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
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| D | X86SchedSandyBridge.td | 1 //=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=//
9 // This file defines the machine model for Sandy Bridge to support instruction
37 // Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
191 // NOTE: These don't exist on Sandy Bridge. Ports are guesses.
1111 // section "Sandy Bridge and Ivy Bridge Pipeline" > "Register allocation and
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| /external/mesa3d/docs/ |
| D | index.rst | 155 Intel Sandy Bridge and Ivy Bridge is the only driver to support OpenGL
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| /external/angle/ |
| D | CONTRIBUTORS | 27 Henry Bridge
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| /external/tensorflow/tensorflow/compiler/mlir/tosa/ |
| D | BUILD | 1 # TensorFlow -> TOSA Compiler Bridge.
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