1 /* 2 * Copyright (c) 2015-2021, Renesas Electronics Corporation. 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #define RCAR_DDR_VERSION "rev.0.41" 9 #define DRAM_CH_CNT 0x04 10 #define SLICE_CNT 0x04 11 #define CS_CNT 0x02 12 13 /* order : CS0A, CS0B, CS1A, CS1B */ 14 #define CSAB_CNT (CS_CNT * 2) 15 16 /* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */ 17 #define CHAB_CNT (DRAM_CH_CNT * 2) 18 19 /* pll setting */ 20 #define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) 21 #define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb))) 22 23 /* for ddr deisity setting */ 24 #define DBMEMCONF_REG(d3, row, bank, col, dw) \ 25 (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw)) 26 27 #define DBMEMCONF_REGD(density) \ 28 (DBMEMCONF_REG((density) % 2, ((density) + 1) / \ 29 2 + (29 - 3 - 10 - 2), 3, 10, 2)) 30 31 #define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) 32 33 /* refresh mode */ 34 #define DBSC_REFINTS (0x0) 35 36 /* system registers */ 37 #define CPG_FRQCRB (CPG_BASE + 0x0004U) 38 39 #define CPG_PLLECR (CPG_BASE + 0x00D0U) 40 #define CPG_MSTPSR5 (CPG_BASE + 0x003CU) 41 #define CPG_SRCR4 (CPG_BASE + 0x00BCU) 42 #define CPG_PLL3CR (CPG_BASE + 0x00DCU) 43 #define CPG_ZB3CKCR (CPG_BASE + 0x0380U) 44 #define CPG_FRQCRD (CPG_BASE + 0x00E4U) 45 #define CPG_SMSTPCR5 (CPG_BASE + 0x0144U) 46 #define CPG_CPGWPR (CPG_BASE + 0x0900U) 47 #define CPG_SRSTCLR4 (CPG_BASE + 0x0950U) 48 49 #define CPG_FRQCRB_KICK_BIT BIT(31) 50 #define CPG_PLLECR_PLL3E_BIT BIT(3) 51 #define CPG_PLLECR_PLL3ST_BIT BIT(11) 52 #define CPG_ZB3CKCR_ZB3ST_BIT BIT(11) 53 54 #define RST_BASE (0xE6160000U) 55 #define RST_MODEMR (RST_BASE + 0x0060U) 56 57 #define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x)) 58 59 /* DBSC registers */ 60 #include "../ddr_regs.h" 61 62 #define DBSC_DBMONCONF4 0xE6793010U 63 64 #define DBSC_PLL_LOCK(ch) (0xE6794054U + 0x100U * (ch)) 65 #define DBSC_PLL_LOCK_0 0xE6794054U 66 #define DBSC_PLL_LOCK_1 0xE6794154U 67 #define DBSC_PLL_LOCK_2 0xE6794254U 68 #define DBSC_PLL_LOCK_3 0xE6794354U 69 70 /* STAT registers */ 71 #define MSTAT_SL_INIT 0xE67E8000U 72 #define MSTAT_REF_ARS 0xE67E8004U 73 #define MSTATQ_STATQC 0xE67E8008U 74 #define MSTATQ_WTENABLE 0xE67E8030U 75 #define MSTATQ_WTREFRESH 0xE67E8034U 76 #define MSTATQ_WTSETTING0 0xE67E8038U 77 #define MSTATQ_WTSETTING1 0xE67E803CU 78 79 #define QOS_BASE1 (0xE67F0000U) 80 #define QOSCTRL_RAS (QOS_BASE1 + 0x0000U) 81 #define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U) 82 #define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U) 83 #define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U) 84 #define QOSCTRL_DANN (QOS_BASE1 + 0x0030U) 85 #define QOSCTRL_DANT (QOS_BASE1 + 0x0038U) 86 #define QOSCTRL_EC (QOS_BASE1 + 0x003CU) 87 #define QOSCTRL_EMS (QOS_BASE1 + 0x0040U) 88 #define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U) 89 #define QOSCTRL_BERR (QOS_BASE1 + 0x0054U) 90 #define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U) 91 #define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U) 92 93 /* other module */ 94 #define THS1_THCTR 0xE6198020U 95 #define THS1_TEMP 0xE6198028U 96