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Searched refs:CondReg (Results 1 – 25 of 25) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FlagsCopyLowering.cpp786 unsigned &CondReg = CondRegs[Cond]; in getCondOrInverseInReg() local
788 if (!CondReg && !InvCondReg) in getCondOrInverseInReg()
789 CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, Cond); in getCondOrInverseInReg()
791 if (CondReg) in getCondOrInverseInReg()
792 return {CondReg, false}; in getCondOrInverseInReg()
841 unsigned &CondReg = CondRegs[Cond]; in rewriteArithmetic() local
842 if (!CondReg) in rewriteArithmetic()
843 CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, Cond); in rewriteArithmetic()
852 .addReg(CondReg) in rewriteArithmetic()
868 unsigned CondReg; in rewriteCMov() local
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DX86FastISel.cpp2102 unsigned CondReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local
2103 if (CondReg == 0) in X86FastEmitCMoveSelect()
2108 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) { in X86FastEmitCMoveSelect()
2109 unsigned KCondReg = CondReg; in X86FastEmitCMoveSelect()
2110 CondReg = createResultReg(&X86::GR32RegClass); in X86FastEmitCMoveSelect()
2112 TII.get(TargetOpcode::COPY), CondReg) in X86FastEmitCMoveSelect()
2114 CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, /*Kill=*/true, in X86FastEmitCMoveSelect()
2118 .addReg(CondReg, getKillRegState(CondIsKill)) in X86FastEmitCMoveSelect()
2320 unsigned CondReg = getRegForValue(Cond); in X86FastEmitPseudoSelect() local
2321 if (CondReg == 0) in X86FastEmitPseudoSelect()
[all …]
DX86InstructionSelector.cpp1408 const Register CondReg = I.getOperand(0).getReg(); in selectCondBranch() local
1413 .addReg(CondReg) in selectCondBranch()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInsertSkips.cpp348 const unsigned CondReg = TRI->getVCC(); in optimizeVccBranch() local
361 if (A->modifiesRegister(CondReg, TRI)) { in optimizeVccBranch()
362 if (!A->definesRegister(CondReg, TRI) || A->getOpcode() != And) in optimizeVccBranch()
366 ReadsCond |= A->readsRegister(CondReg, TRI); in optimizeVccBranch()
408 MI.killsRegister(CondReg, TRI)) in optimizeVccBranch()
423 MI.RemoveOperand(MI.findRegisterUseOperandIdx(CondReg, false /*Kill*/, TRI)); in optimizeVccBranch()
DSIOptimizeExecMaskingPreRA.cpp198 const unsigned CondReg = Wave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; in optimizeVcndVcmpPair() local
208 auto *And = TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister, in optimizeVcndVcmpPair()
272 (CmpReg == CondReg && in optimizeVcndVcmpPair()
275 return MI.readsRegister(CondReg, TRI); in optimizeVcndVcmpPair()
DAMDGPURegisterBankInfo.cpp835 Register CondReg; in executeInWaterfallLoop() local
860 bool First = CondReg == AMDGPU::NoRegister; in executeInWaterfallLoop()
862 CondReg = NewCondReg; in executeInWaterfallLoop()
878 .addReg(CondReg); in executeInWaterfallLoop()
879 CondReg = AndReg; in executeInWaterfallLoop()
955 bool First = CondReg == AMDGPU::NoRegister; in executeInWaterfallLoop()
957 CondReg = NewCondReg; in executeInWaterfallLoop()
971 .addReg(CondReg); in executeInWaterfallLoop()
972 CondReg = AndReg; in executeInWaterfallLoop()
997 .addReg(CondReg, RegState::Kill); in executeInWaterfallLoop()
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DAMDGPUInstructionSelector.cpp1579 Register CondReg = CondOp.getReg(); in selectG_BRCOND() local
1591 if (!isVCC(CondReg, *MRI)) { in selectG_BRCOND()
1592 if (MRI->getType(CondReg) != LLT::scalar(32)) in selectG_BRCOND()
1610 if (!MRI->getRegClassOrNull(CondReg)) in selectG_BRCOND()
1611 MRI->setRegClass(CondReg, ConstrainRC); in selectG_BRCOND()
1614 .addReg(CondReg); in selectG_BRCOND()
DSIInstrInfo.cpp2048 static void preserveCondRegFlags(MachineOperand &CondReg, in preserveCondRegFlags() argument
2050 CondReg.setIsUndef(OrigCond.isUndef()); in preserveCondRegFlags()
2051 CondReg.setIsKill(OrigCond.isKill()); in preserveCondRegFlags()
2102 MachineOperand &CondReg = CondBr->getOperand(1); in insertBranch() local
2103 CondReg.setIsUndef(Cond[1].isUndef()); in insertBranch()
2104 CondReg.setIsKill(Cond[1].isKill()); in insertBranch()
DAMDGPUMachineCFGStructurizer.cpp1896 Register CondReg = Cond[0].getReg(); in ensureCondIsNotKilled() local
1897 for (auto UI = MRI->use_begin(CondReg), E = MRI->use_end(); UI != E; ++UI) { in ensureCondIsNotKilled()
DAMDGPUISelDAGToDAG.cpp2069 unsigned CondReg = UseSCCBr ? (unsigned)AMDGPU::SCC : TRI->getVCC(); in SelectBRCOND() local
2096 SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, CondReg, Cond); in SelectBRCOND()
DSIISelLowering.cpp3193 Register CondReg = MRI.createVirtualRegister(BoolRC); in emitLoadM0FromVGPRLoop() local
3212 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg) in emitLoadM0FromVGPRLoop()
3220 .addReg(CondReg, RegState::Kill); in emitLoadM0FromVGPRLoop()
3222 MRI.setSimpleHint(NewExec, CondReg); in emitLoadM0FromVGPRLoop()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyFastISel.cpp891 unsigned CondReg = getRegForI1Value(Select->getCondition(), Not); in selectSelect() local
892 if (CondReg == 0) in selectSelect()
940 .addReg(CondReg); in selectSelect()
1281 unsigned CondReg = getRegForI1Value(Br->getCondition(), Not); in selectBr() local
1282 if (CondReg == 0) in selectBr()
1291 .addReg(CondReg); in selectBr()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyFastISel.cpp720 unsigned CondReg = getRegForI1Value(Select->getCondition(), Not); in selectSelect() local
721 if (CondReg == 0) in selectSelect()
765 .addReg(CondReg); in selectSelect()
1096 unsigned CondReg = getRegForI1Value(Br->getCondition(), Not); in selectBr() local
1104 .addReg(CondReg); in selectBr()
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp926 unsigned CondReg = createResultReg(&Mips::GPR32RegClass); in selectBranch() local
927 if (!emitCmp(CondReg, CI)) in selectBranch()
930 .addReg(CondReg) in selectBranch()
996 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
998 if (!Src1Reg || !Src2Reg || !CondReg) in selectSelect()
1005 if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true)) in selectSelect()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsFastISel.cpp970 unsigned CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
971 if (CondReg == 0) in selectBranch()
974 ZExtCondReg = emitIntExt(MVT::i1, CondReg, MVT::i32, true); in selectBranch()
1049 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
1051 if (!Src1Reg || !Src2Reg || !CondReg) in selectSelect()
1058 if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true)) in selectSelect()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp776 auto CondReg = MIB->getOperand(1).getReg(); in selectSelect() local
777 assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) && in selectSelect()
780 .addUse(CondReg) in selectSelect()
DARMFastISel.cpp1623 unsigned CondReg = getRegForValue(I->getOperand(0)); in SelectSelect() local
1624 if (CondReg == 0) return false; in SelectSelect()
1650 CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0); in SelectSelect()
1653 .addReg(CondReg) in SelectSelect()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp2381 unsigned CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2382 if (!CondReg) in selectBranch()
2395 unsigned CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2396 if (CondReg == 0) in selectBranch()
2409 = constrainOperandRegClass(II, CondReg, II.getNumDefs()); in selectBranch()
2621 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
2622 if (!CondReg) in selectSelect()
2673 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
2674 if (!CondReg) in selectSelect()
2679 CondReg = constrainOperandRegClass(II, CondReg, 1); in selectSelect()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp2512 unsigned CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2513 if (!CondReg) in selectBranch()
2526 unsigned CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2527 if (CondReg == 0) in selectBranch()
2540 = constrainOperandRegClass(II, CondReg, II.getNumDefs()); in selectBranch()
2752 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
2753 if (!CondReg) in selectSelect()
2804 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
2805 if (!CondReg) in selectSelect()
2810 CondReg = constrainOperandRegClass(II, CondReg, 1); in selectSelect()
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DAArch64InstructionSelector.cpp983 const Register CondReg = I.getOperand(0).getReg(); in selectCompareBranch() local
985 MachineInstr *CCMI = MRI.getVRegDef(CondReg); in selectCompareBranch()
1500 const Register CondReg = I.getOperand(0).getReg(); in select() local
1513 .addUse(CondReg) in select()
1522 .addUse(CondReg) in select()
2260 const Register CondReg = I.getOperand(1).getReg(); in select() local
2271 .addUse(CondReg) in select()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp1618 unsigned CondReg = getRegForValue(I->getOperand(0)); in SelectSelect() local
1619 if (CondReg == 0) return false; in SelectSelect()
1645 CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0); in SelectSelect()
1648 .addReg(CondReg) in SelectSelect()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp2023 unsigned CondReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local
2024 if (CondReg == 0) in X86FastEmitCMoveSelect()
2029 .addReg(CondReg, getKillRegState(CondIsKill)).addImm(1); in X86FastEmitCMoveSelect()
2196 unsigned CondReg = getRegForValue(Cond); in X86FastEmitPseudoSelect() local
2197 if (CondReg == 0) in X86FastEmitPseudoSelect()
2201 .addReg(CondReg, getKillRegState(CondIsKill)).addImm(1); in X86FastEmitPseudoSelect()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp783 unsigned CondReg = createResultReg(&PPC::CRRCRegClass); in SelectBranch() local
786 CondReg)) in SelectBranch()
790 .addImm(PPCPred).addReg(CondReg).addMBB(TBB); in SelectBranch()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp2662 Register CondReg = MI.getOperand(1).getReg(); in fewerElementsVectorSelect() local
2668 LLT CondTy = MRI.getType(CondReg); in fewerElementsVectorSelect()
2716 MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg, in fewerElementsVectorSelect()
3683 Register CondReg = MI.getOperand(1).getReg(); in narrowScalarSelect() local
3684 LLT CondTy = MRI.getType(CondReg); in narrowScalarSelect()
3706 CondReg, Src1Regs[I], Src2Regs[I]); in narrowScalarSelect()
3712 LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]); in narrowScalarSelect()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp790 unsigned CondReg = createResultReg(&PPC::CRRCRegClass); in SelectBranch() local
793 CondReg, PPCPred)) in SelectBranch()
798 .addReg(CondReg).addMBB(TBB); in SelectBranch()