/external/llvm/lib/Transforms/InstCombine/ |
D | InstCombineMulDivRem.cpp | 1227 bool Cvt = FpVal.getExactInverse(&Reciprocal); in CvtFDivConstToReciprocal() local 1229 if (!Cvt && AllowReciprocal && FpVal.isFiniteNonZero()) { in CvtFDivConstToReciprocal() 1232 Cvt = !Reciprocal.isDenormal(); in CvtFDivConstToReciprocal() 1235 if (!Cvt) in CvtFDivConstToReciprocal()
|
/external/swiftshader/third_party/subzero/src/ |
D | IceTargetLoweringX8664.h | 526 void _cvt(Variable *Dest, Operand *Src0, Insts::Cvt::CvtVariant Variant) { in _cvt() 527 Context.insert<Insts::Cvt>(Dest, Src0, Variant); in _cvt()
|
D | IceTargetLoweringX8632.h | 530 void _cvt(Variable *Dest, Operand *Src0, Insts::Cvt::CvtVariant Variant) { in _cvt() 531 Context.insert<Insts::Cvt>(Dest, Src0, Variant); in _cvt()
|
D | IceTargetLoweringX8664.cpp | 2508 _cvt(T, Src0RM, Insts::Cvt::Float2float); in lowerCast() 2518 _cvt(T, Src0R, Insts::Cvt::Tps2dq); in lowerCast() 2537 _cvt(T_1, Src0RM, Insts::Cvt::Tss2si); in lowerCast() 2566 _cvt(T_1, Src0RM, Insts::Cvt::Tss2si); in lowerCast() 2579 _cvt(T, Src0R, Insts::Cvt::Dq2ps); in lowerCast() 2597 _cvt(T_2, T_1, Insts::Cvt::Si2ss); in lowerCast() 2623 _cvt(T_2, T_1, Insts::Cvt::Si2ss); in lowerCast() 3783 _cvt(T, Src0R, Insts::Cvt::Ps2dq); in lowerIntrinsic() 3802 _cvt(T_1, Src0RM, Insts::Cvt::Ss2si); in lowerIntrinsic()
|
D | IceTargetLoweringX8632.cpp | 2764 _cvt(T, Src0RM, Insts::Cvt::Float2float); in lowerCast() 2774 _cvt(T, Src0R, Insts::Cvt::Tps2dq); in lowerCast() 2791 _cvt(T_1, Src0RM, Insts::Cvt::Tss2si); in lowerCast() 2816 _cvt(T_1, Src0RM, Insts::Cvt::Tss2si); in lowerCast() 2829 _cvt(T, Src0R, Insts::Cvt::Dq2ps); in lowerCast() 2845 _cvt(T_2, T_1, Insts::Cvt::Si2ss); in lowerCast() 2869 _cvt(T_2, T_1, Insts::Cvt::Si2ss); in lowerCast() 4253 _cvt(T, Src0R, Insts::Cvt::Ps2dq); in lowerIntrinsic() 4269 _cvt(T_1, Src0RM, Insts::Cvt::Ss2si); in lowerIntrinsic()
|
D | IceInstX8632.h | 213 Cvt, enumerator 2587 return InstX86Base::isClassof(Instr, InstX86Base::Cvt); in classof() 3256 using Cvt = InstX86Cvt; member
|
D | IceInstX8664.h | 154 Cvt, enumerator 2528 return InstX86Base::isClassof(Instr, InstX86Base::Cvt); in classof() 3155 using Cvt = InstX86Cvt; member
|
D | IceInstX8632.cpp | 285 : InstX86Base(Func, InstX86Base::Cvt, 1, Dest), Variant(Variant) { in InstX86Cvt()
|
D | IceInstX8664.cpp | 273 : InstX86Base(Func, InstX86Base::Cvt, 1, Dest), Variant(Variant) { in InstX86Cvt()
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIISelLowering.cpp | 4292 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_PKRTZ_F16_F32, SL, MVT::i32, in ReplaceNodeResults() local 4294 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Cvt)); in ReplaceNodeResults() 4319 SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1); in ReplaceNodeResults() local 4320 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, Cvt)); in ReplaceNodeResults() 7317 SDValue Cvt = NewLoad; in widenLoad() local 7319 Cvt = DAG.getNode(ISD::SIGN_EXTEND_INREG, SL, MVT::i32, NewLoad, in widenLoad() 7323 Cvt = DAG.getZeroExtendInReg(NewLoad, SL, TruncVT); in widenLoad() 7331 DCI.AddToWorklist(Cvt.getNode()); in widenLoad() 7335 Cvt = getLoadExtOrTrunc(DAG, Ld->getExtensionType(), Cvt, SL, IntVT); in widenLoad() 7336 DCI.AddToWorklist(Cvt.getNode()); in widenLoad() [all …]
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
D | NVPTXISelDAGToDAG.cpp | 2320 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_u32_u16, DL, in tryStoreParam() local 2322 Ops[0] = SDValue(Cvt, 0); in tryStoreParam() 2329 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_s32_s16, DL, in tryStoreParam() local 2331 Ops[0] = SDValue(Cvt, 0); in tryStoreParam()
|
/external/llvm/lib/Target/NVPTX/ |
D | NVPTXISelDAGToDAG.cpp | 3108 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_u32_u16, DL, in tryStoreParam() local 3110 Ops[0] = SDValue(Cvt, 0); in tryStoreParam() 3117 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_s32_s16, DL, in tryStoreParam() local 3119 Ops[0] = SDValue(Cvt, 0); in tryStoreParam()
|
/external/llvm/lib/Target/AMDGPU/ |
D | SIISelLowering.cpp | 2432 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src); in performUCharToFloatCombine() local 2433 DCI.AddToWorklist(Cvt.getNode()); in performUCharToFloatCombine() 2434 return Cvt; in performUCharToFloatCombine()
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 5785 SDValue Cvt = DAG.getNode(ARMISD::VMOVrh, SDLoc(Op), MVT::i32, Op); in ExpandBITCAST() local 5786 DAG.ReplaceAllUsesWith(*ZeroExtend, &Cvt); in ExpandBITCAST() 5787 return Cvt; in ExpandBITCAST() 5812 SDValue Cvt; in ExpandBITCAST() local 5815 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST() 5819 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST() 5822 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); in ExpandBITCAST()
|
/external/swiftshader/third_party/subzero/unittest/AssemblerX8632/ |
D | XmmArith.cpp | 1350 TEST_F(AssemblerX8632Test, Cvt) { in TEST_F() argument
|
/external/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
D | XmmArith.cpp | 1424 TEST_F(AssemblerX8664Test, Cvt) { in TEST_F() argument
|
/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 4484 SDValue Cvt; in ExpandBITCAST() local 4487 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST() 4491 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST() 4494 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); in ExpandBITCAST()
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 18769 SDValue Cvt = DAG.getSelect(DL, MVT::v4f32, IsNeg, Slow, SignCvt); in lowerINT_TO_FP_vXi64() local 18772 return DAG.getMergeValues({Cvt, Chain}, DL); in lowerINT_TO_FP_vXi64() 18774 return Cvt; in lowerINT_TO_FP_vXi64() 29211 SDValue Cvt = DAG.getSelect(dl, MVT::v4f32, IsNeg, Slow, SignCvt); in ReplaceNodeResults() local 29212 Results.push_back(Cvt); in ReplaceNodeResults()
|
/external/ComputeLibrary/data/images/ |
D | 800x600.ppm | 3985 …)��6��>kj��:��V��Zrp&��O��B��7x|/��@��y��x��Qqu(^^��L��\��A��W��I��F��d��Cvt)ur,��I��SGB jf+��qTQ
|