Searched refs:DBSC_DBTR (Results 1 – 2 of 2) sorted by relevance
| /external/arm-trusted-firmware/drivers/renesas/common/ddr/ddr_b/ |
| D | boot_init_dram.c | 2058 mmio_write_32(DBSC_DBTR(0), RL); in dbsc_regset()
2061 mmio_write_32(DBSC_DBTR(1), WL); in dbsc_regset()
2064 mmio_write_32(DBSC_DBTR(2), 0); in dbsc_regset()
2067 mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]); in dbsc_regset()
2070 mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]); in dbsc_regset()
2073 mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]); in dbsc_regset()
2076 mmio_write_32(DBSC_DBTR(6), js2[js2_tras]); in dbsc_regset()
2079 mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]); in dbsc_regset()
2082 mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]); in dbsc_regset()
2085 mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]); in dbsc_regset()
[all …]
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| /external/arm-trusted-firmware/drivers/renesas/common/ |
| D | ddr_regs.h | 44 #define DBSC_DBTR(x) (0xE6790300U + 0x04U * (x)) macro
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