/external/libavc/common/arm/ |
D | ih264_arm_memory_barrier.s | 62 @* Description : Adds DMB
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/external/llvm/test/MC/ARM/ |
D | invalid-barrier.s | 5 @ DMB
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D | basic-arm-instructions-v8.s | 20 @ DMB (v8 barriers)
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D | basic-thumb2-instructions-v8.s | 50 @ DMB (ARMv8-only barriers)
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMOptimizeBarriersPass.cpp | 67 if (MI.getOpcode() == ARM::DMB) { in runOnMachineFunction()
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D | ARMScheduleA57.td | 130 "(t2)?CPS[123]p$", "(t2)?DBG$", "(t2)?DMB$", "(t2)?DSB$", "ERET$",
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/external/llvm/lib/Target/ARM/ |
D | ARMOptimizeBarriersPass.cpp | 70 if (MI.getOpcode() == ARM::DMB) { in runOnMachineFunction()
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/external/llvm/test/CodeGen/AArch64/ |
D | atomic-ops-not-barriers.ll | 20 ; simple_ver basic block, which LLVM attempted to do when DMB had been marked
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D | intrinsics-memory-barrier.ll | 18 ; instructions around DMB.
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/external/llvm/test/CodeGen/ARM/ |
D | intrinsics-memory-barrier.ll | 13 ; instructions around DMB.
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D | atomic-ops-v8.ll | 1417 ; simple_ver basic block, which LLVM attempted to do when DMB had been marked
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrAtomics.td | 17 def : Pat<(atomic_fence (i64 4), (imm)), (DMB (i32 0x9))>; 18 def : Pat<(atomic_fence (imm), (imm)), (DMB (i32 0xb))>;
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D | AArch64SchedCyclone.td | 292 // SLREX,DMB,DSB
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D | AArch64SystemOperands.td | 52 // DMB/DSB (data barrier) instruction options.
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64InstrAtomics.td | 19 def : Pat<(atomic_fence (i64 4), (timm)), (DMB (i32 0x9))>; 20 def : Pat<(atomic_fence (timm), (timm)), (DMB (i32 0xb))>;
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D | AArch64SchedCyclone.td | 293 // SLREX,DMB,DSB
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D | AArch64SchedFalkorDetails.td | 1244 def : InstRW<[FalkorWr_1LD_0cyc], (instrs CLREX, DMB, DSB)>;
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/external/OpenCSD/decoder/tests/snapshots/TC2/ds5-dumps/ |
D | etmv3_0x10.txt | 37 Instruction 31 S:0xC004EFA2 0xF3BF8F5F 1 DMB false 57 Instruction 48 S:0xC004EFD0 0xF3BF8F5F 1 DMB false 204 Instruction 185 S:0xC004EFA2 0xF3BF8F5F 8 DMB false 224 Instruction 202 S:0xC004EFD0 0xF3BF8F5F 1 DMB false 451 Instruction 421 S:0xC0025E50 0xF3BF8F5F 1 DMB false 763 Instruction 714 S:0xC00361F8 0xF3BF8F5F 1 DMB false 777 Instruction 726 S:0xC003621C 0xF3BF8F5F 1 DMB false 876 Instruction 818 S:0xC004EFA2 0xF3BF8F5F 1 DMB false 896 Instruction 835 S:0xC004EFD0 0xF3BF8F5F 1 DMB false 1229 Instruction 1133 S:0xC002D9C6 0xF3BF8F5F 20 DMB false [all …]
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D | ptmv1_0x13.txt | 40 Instruction 27 S:0xC0018DAE 0xF3BF8F5F 0 DMB false 190 Instruction 167 S:0xC004F554 0xF3BF8F5F 0 DMB false 240 Instruction 215 S:0xC004F5F8 0xF3BF8F5F 0 DMB false 313 Instruction 288 S:0xC004F554 0xF3BF8F5F 0 DMB false 363 Instruction 336 S:0xC004F5F8 0xF3BF8F5F 0 DMB false 1115 Instruction 1051 S:0xC004EFA2 0xF3BF8F5F 0 DMB false 1134 Instruction 1068 S:0xC004EFD0 0xF3BF8F5F 0 DMB false 1332 Instruction 1262 S:0xC004F554 0xF3BF8F5F 0 DMB false 1382 Instruction 1310 S:0xC004F5F8 0xF3BF8F5F 0 DMB false 1525 Instruction 1453 S:0xC003C07A 0xF3BF8F5F 0 DMB false [all …]
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D | etmv3_0x11.txt | 37 Instruction 33 S:0xC0050984 0xF3BF8F5F 1 DMB false 85 Instruction 79 S:0xC00509A2 0xF3BF8F5F 3 DMB false 118 Instruction 110 S:0xC0055608 0xF3BF8F5F 1 DMB false 122 Instruction 114 S:0xC0055616 0xF3BF8F5F 1 DMB false 364 Instruction 348 S:0xC003D484 0xF3BF8F5F 1 DMB false 385 Instruction 367 S:0xC003D4B4 0xF3BF8F5F 8 DMB false 404 Instruction 386 S:0xC003F8D0 0xF3BF8F5F 3 DMB false 969 Instruction 939 S:0xC003F7F8 0xF3BF8F5F 1 DMB false 2003 Instruction 1960 S:0xC003D578 0xF3BF8F5F 27 DMB false 2823 Instruction 2763 S:0xC003CC52 0xF3BF8F5F 13 DMB false [all …]
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D | etmv3_0x12.txt | 432 Instruction 416 S:0xC003F7F8 0xF3BF8F5F 1 DMB false 993 Instruction 968 S:0xC003CC52 0xF3BF8F5F 13 DMB false 1372 Instruction 1339 S:0xC00359EC 0xF3BF8F5F 1 DMB false 1440 Instruction 1407 S:0xC004F554 0xF3BF8F5F 1 DMB false 1491 Instruction 1455 S:0xC004F5F8 0xF3BF8F5F 1 DMB false 1770 Instruction 1725 S:0xC0025BD6 0xF3BF8F5F 1 DMB false
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/external/OpenCSD/decoder/tests/snapshots/juno_r1_1/ds-5-dumps/ |
D | Trace_Report_0x11_cpu_1_2015Sep17_104748.txt | 87 EL1N:0xFFFFFFC0000C5800 D5033BBF DMB ISH
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D | Trace_Report_0x13_cpu_3_2015Sep17_104147.txt | 264 EL1N:0xFFFFFFC0000C5800 D5033BBF DMB ISH
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/external/vixl/src/aarch64/ |
D | constants-aarch64.h | 960 DMB = MemBarrierFixed | 0x00000020, enumerator
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/external/capstone/arch/ARM/ |
D | ARMGenAsmWriter.inc | 115 54005U, // DMB 2919 0U, // DMB 6154 // DMB, DSB 8823 // (DMB 15)
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