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Searched refs:DMB (Results 1 – 25 of 66) sorted by relevance

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/external/libavc/common/arm/
Dih264_arm_memory_barrier.s62 @* Description : Adds DMB
/external/llvm/test/MC/ARM/
Dinvalid-barrier.s5 @ DMB
Dbasic-arm-instructions-v8.s20 @ DMB (v8 barriers)
Dbasic-thumb2-instructions-v8.s50 @ DMB (ARMv8-only barriers)
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMOptimizeBarriersPass.cpp67 if (MI.getOpcode() == ARM::DMB) { in runOnMachineFunction()
DARMScheduleA57.td130 "(t2)?CPS[123]p$", "(t2)?DBG$", "(t2)?DMB$", "(t2)?DSB$", "ERET$",
/external/llvm/lib/Target/ARM/
DARMOptimizeBarriersPass.cpp70 if (MI.getOpcode() == ARM::DMB) { in runOnMachineFunction()
/external/llvm/test/CodeGen/AArch64/
Datomic-ops-not-barriers.ll20 ; simple_ver basic block, which LLVM attempted to do when DMB had been marked
Dintrinsics-memory-barrier.ll18 ; instructions around DMB.
/external/llvm/test/CodeGen/ARM/
Dintrinsics-memory-barrier.ll13 ; instructions around DMB.
Datomic-ops-v8.ll1417 ; simple_ver basic block, which LLVM attempted to do when DMB had been marked
/external/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td17 def : Pat<(atomic_fence (i64 4), (imm)), (DMB (i32 0x9))>;
18 def : Pat<(atomic_fence (imm), (imm)), (DMB (i32 0xb))>;
DAArch64SchedCyclone.td292 // SLREX,DMB,DSB
DAArch64SystemOperands.td52 // DMB/DSB (data barrier) instruction options.
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td19 def : Pat<(atomic_fence (i64 4), (timm)), (DMB (i32 0x9))>;
20 def : Pat<(atomic_fence (timm), (timm)), (DMB (i32 0xb))>;
DAArch64SchedCyclone.td293 // SLREX,DMB,DSB
DAArch64SchedFalkorDetails.td1244 def : InstRW<[FalkorWr_1LD_0cyc], (instrs CLREX, DMB, DSB)>;
/external/OpenCSD/decoder/tests/snapshots/TC2/ds5-dumps/
Detmv3_0x10.txt37 Instruction 31 S:0xC004EFA2 0xF3BF8F5F 1 DMB false
57 Instruction 48 S:0xC004EFD0 0xF3BF8F5F 1 DMB false
204 Instruction 185 S:0xC004EFA2 0xF3BF8F5F 8 DMB false
224 Instruction 202 S:0xC004EFD0 0xF3BF8F5F 1 DMB false
451 Instruction 421 S:0xC0025E50 0xF3BF8F5F 1 DMB false
763 Instruction 714 S:0xC00361F8 0xF3BF8F5F 1 DMB false
777 Instruction 726 S:0xC003621C 0xF3BF8F5F 1 DMB false
876 Instruction 818 S:0xC004EFA2 0xF3BF8F5F 1 DMB false
896 Instruction 835 S:0xC004EFD0 0xF3BF8F5F 1 DMB false
1229 Instruction 1133 S:0xC002D9C6 0xF3BF8F5F 20 DMB false
[all …]
Dptmv1_0x13.txt40 Instruction 27 S:0xC0018DAE 0xF3BF8F5F 0 DMB false
190 Instruction 167 S:0xC004F554 0xF3BF8F5F 0 DMB false
240 Instruction 215 S:0xC004F5F8 0xF3BF8F5F 0 DMB false
313 Instruction 288 S:0xC004F554 0xF3BF8F5F 0 DMB false
363 Instruction 336 S:0xC004F5F8 0xF3BF8F5F 0 DMB false
1115 Instruction 1051 S:0xC004EFA2 0xF3BF8F5F 0 DMB false
1134 Instruction 1068 S:0xC004EFD0 0xF3BF8F5F 0 DMB false
1332 Instruction 1262 S:0xC004F554 0xF3BF8F5F 0 DMB false
1382 Instruction 1310 S:0xC004F5F8 0xF3BF8F5F 0 DMB false
1525 Instruction 1453 S:0xC003C07A 0xF3BF8F5F 0 DMB false
[all …]
Detmv3_0x11.txt37 Instruction 33 S:0xC0050984 0xF3BF8F5F 1 DMB false
85 Instruction 79 S:0xC00509A2 0xF3BF8F5F 3 DMB false
118 Instruction 110 S:0xC0055608 0xF3BF8F5F 1 DMB false
122 Instruction 114 S:0xC0055616 0xF3BF8F5F 1 DMB false
364 Instruction 348 S:0xC003D484 0xF3BF8F5F 1 DMB false
385 Instruction 367 S:0xC003D4B4 0xF3BF8F5F 8 DMB false
404 Instruction 386 S:0xC003F8D0 0xF3BF8F5F 3 DMB false
969 Instruction 939 S:0xC003F7F8 0xF3BF8F5F 1 DMB false
2003 Instruction 1960 S:0xC003D578 0xF3BF8F5F 27 DMB false
2823 Instruction 2763 S:0xC003CC52 0xF3BF8F5F 13 DMB false
[all …]
Detmv3_0x12.txt432 Instruction 416 S:0xC003F7F8 0xF3BF8F5F 1 DMB false
993 Instruction 968 S:0xC003CC52 0xF3BF8F5F 13 DMB false
1372 Instruction 1339 S:0xC00359EC 0xF3BF8F5F 1 DMB false
1440 Instruction 1407 S:0xC004F554 0xF3BF8F5F 1 DMB false
1491 Instruction 1455 S:0xC004F5F8 0xF3BF8F5F 1 DMB false
1770 Instruction 1725 S:0xC0025BD6 0xF3BF8F5F 1 DMB false
/external/OpenCSD/decoder/tests/snapshots/juno_r1_1/ds-5-dumps/
DTrace_Report_0x11_cpu_1_2015Sep17_104748.txt87 EL1N:0xFFFFFFC0000C5800 D5033BBF DMB ISH
DTrace_Report_0x13_cpu_3_2015Sep17_104147.txt264 EL1N:0xFFFFFFC0000C5800 D5033BBF DMB ISH
/external/vixl/src/aarch64/
Dconstants-aarch64.h960 DMB = MemBarrierFixed | 0x00000020, enumerator
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc115 54005U, // DMB
2919 0U, // DMB
6154 // DMB, DSB
8823 // (DMB 15)

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