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Searched refs:DefRC (Results 1 – 21 of 21) sorted by relevance

/external/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp290 const TargetRegisterClass *DefRC, in shareSameRegisterFile() argument
295 if (DefRC == SrcRC) in shareSameRegisterFile()
301 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
309 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
314 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
317 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
320 bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
325 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
DDetectDeadLanes.cpp376 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes() local
390 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) { in determineInitialDefinedLanes()
DPeepholeOptimizer.cpp624 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in findNextSource() local
685 ShouldRewrite = TRI->shouldRewriteCopySrc(DefRC, SubReg, SrcRC, in findNextSource()
938 const TargetRegisterClass *DefRC = MRI.getRegClass(Def.Reg); in RewriteSource() local
939 unsigned NewVR = MRI.createVirtualRegister(DefRC); in RewriteSource()
DRegisterCoalescer.cpp930 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF); in reMaterializeTrivialDef() local
942 if (!DefRC->contains(NewDstReg)) in reMaterializeTrivialDef()
973 TRI->getCommonSubClass(DefRC, DstRC); in reMaterializeTrivialDef()
1021 if (DefRC != nullptr) { in reMaterializeTrivialDef()
1023 NewRC = TRI->getMatchingSuperRegClass(NewRC, DefRC, NewIdx); in reMaterializeTrivialDef()
1025 NewRC = TRI->getCommonSubClass(NewRC, DefRC); in reMaterializeTrivialDef()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp343 const TargetRegisterClass *DefRC, in shareSameRegisterFile() argument
348 if (DefRC == SrcRC) in shareSameRegisterFile()
354 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
362 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
367 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
370 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
373 bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
378 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
DDetectDeadLanes.cpp373 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes() local
387 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) { in determineInitialDefinedLanes()
DPeepholeOptimizer.cpp669 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in findNextSource() local
732 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC, in findNextSource()
1232 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource() local
1233 Register NewVReg = MRI->createVirtualRegister(DefRC); in rewriteSource()
DRegisterCoalescer.cpp1284 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF); in reMaterializeTrivialDef() local
1296 if (!DefRC->contains(NewDstReg)) in reMaterializeTrivialDef()
1327 TRI->getCommonSubClass(DefRC, DstRC); in reMaterializeTrivialDef()
1376 if (DefRC != nullptr) { in reMaterializeTrivialDef()
1378 NewRC = TRI->getMatchingSuperRegClass(NewRC, DefRC, NewIdx); in reMaterializeTrivialDef()
1380 NewRC = TRI->getCommonSubClass(NewRC, DefRC); in reMaterializeTrivialDef()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86RegisterInfo.h77 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
DX86RegisterInfo.cpp219 bool X86RegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
226 if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 && in shouldRewriteCopySrc()
230 return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg, in shouldRewriteCopySrc()
DX86SpeculativeLoadHardening.cpp2336 auto *DefRC = MRI->getRegClass(OldDefReg); in hardenPostLoad() local
2341 Register UnhardenedReg = MRI->createVirtualRegister(DefRC); in hardenPostLoad()
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.h135 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
DSIRegisterInfo.cpp808 const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
828 return getCommonSubClass(DefRC, SrcRC) != nullptr; in shouldRewriteCopySrc()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsInstructionSelector.cpp394 const TargetRegisterClass *DefRC = nullptr; in select() local
396 DefRC = TRI.getRegClass(DestReg); in select()
398 DefRC = getRegClassForTypeOnBank(DestReg, MRI); in select()
401 return RBI.constrainGenericRegister(DestReg, *DefRC, MRI); in select()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.h181 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
DAMDGPUInstructionSelector.cpp182 const TargetRegisterClass *DefRC in selectPHI() local
184 if (!DefRC) { in selectPHI()
191 DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB, *MRI); in selectPHI()
192 if (!DefRC) { in selectPHI()
200 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in selectPHI()
DSIRegisterInfo.cpp1467 const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
1487 return getCommonSubClass(DefRC, SrcRC) != nullptr; in shouldRewriteCopySrc()
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h517 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h534 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstructionSelector.cpp1435 const TargetRegisterClass *DefRC in select() local
1437 if (!DefRC) { in select()
1443 DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI); in select()
1444 if (!DefRC) { in select()
1452 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonConstPropagation.cpp1954 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg); in evaluate() local
1955 unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo); in evaluate()
1956 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate()