| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MacroFusion.cpp | 99 if (&SecondSU != &DAG.ExitSU) in fuseInstructionPair()
103 SU == &DAG.ExitSU || SU == &SecondSU || SU->isPred(&SecondSU)) in fuseInstructionPair()
124 if (&SecondSU == &DAG.ExitSU) { in fuseInstructionPair()
161 if (DAG->ExitSU.getInstr()) in apply()
163 scheduleAdjacentImpl(*DAG, DAG->ExitSU); in apply()
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| D | ScheduleDAGInstrs.cpp | 116 … Type::getVoidTy(mf.getFunction().getContext()))), Topo(SUnits, &ExitSU) { in ScheduleDAGInstrs()
202 ExitSU.setInstr(ExitMI); in addSchedBarrierDeps()
209 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg)); in addSchedBarrierDeps()
211 addVRegUseDeps(&ExitSU, ExitMI->getOperandNo(&MO)); in addSchedBarrierDeps()
221 Uses.insert(PhysRegSUOper(&ExitSU, -1, LI.PhysReg)); in addSchedBarrierDeps()
309 if (DefSU == &ExitSU) in addPhysRegDeps()
880 ExitSU.addPred(Dep); in buildSchedGraph()
1173 if (ExitSU.getInstr() != nullptr) in dump()
1174 dumpNodeAll(ExitSU); in dump()
1183 else if (SU == &ExitSU) in getGraphNodeLabel()
[all …]
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| D | ScheduleDAG.cpp | 67 ExitSU = SUnit(); in clearDAG()
357 else if (&SU == &ExitSU) in dumpNodeName()
478 if (ExitSU) in InitDAGTopologicalSorting()
479 WorkList.push_back(ExitSU); in InitDAGTopologicalSorting()
741 : SUnits(sunits), ExitSU(exitsu) {} in ScheduleDAGTopologicalSort()
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| D | MachineScheduler.cpp | 643 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) in releaseSucc()
844 ExitSU.biasCriticalPath(); in findRootsAndBiasEdges()
868 releasePredecessors(&ExitSU); in initQueues()
1116 if (SU.isScheduled || &SU == &ExitSU) in updatePressureDiffs()
1150 if (!SU->isScheduled && SU != &ExitSU) { in updatePressureDiffs()
1184 if (ExitSU.getInstr() != nullptr) in dump()
1185 dumpNodeAll(ExitSU); in dump()
1345 if (SU == &ExitSU) in computeCyclicCriticalPath()
2844 Rem.CriticalPath = DAG->ExitSU.getDepth(); in registerRoots()
3346 Rem.CriticalPath = DAG->ExitSU.getDepth(); in registerRoots()
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| D | PostRASchedulerList.cpp | 484 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) in ReleaseSucc()
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| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAG.cpp | 41 MRI(mf.getRegInfo()), EntrySU(), ExitSU() { in ScheduleDAG()
53 ExitSU = SUnit(); in clearDAG()
468 if (ExitSU) in InitDAGTopologicalSorting()
469 WorkList.push_back(ExitSU); in InitDAGTopologicalSorting()
639 : SUnits(sunits), ExitSU(exitsu) {} in ScheduleDAGTopologicalSort()
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| D | MachineScheduler.cpp | 534 return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU); in canAddEdge()
538 if (SuccSU != &ExitSU) { in addEdge()
577 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) in releaseSucc()
777 ExitSU.biasCriticalPath(); in findRootsAndBiasEdges()
802 releasePredecessors(&ExitSU); in initQueues()
1007 if (SU.isScheduled || &SU == &ExitSU) in updatePressureDiffs()
1044 if (!SU->isScheduled && SU != &ExitSU) { in updatePressureDiffs()
1229 if (SU == &ExitSU) in computeCyclicCriticalPath()
1519 SUnit &ExitSU = DAG->ExitSU; in apply() local
1520 MachineInstr *Branch = ExitSU.getInstr(); in apply()
[all …]
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| D | ScheduleDAGInstrs.cpp | 251 ExitSU.setInstr(ExitMI); in addSchedBarrierDeps()
264 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg)); in addSchedBarrierDeps()
266 addVRegUseDeps(&ExitSU, i); in addSchedBarrierDeps()
276 Uses.insert(PhysRegSUOper(&ExitSU, -1, LI.PhysReg)); in addSchedBarrierDeps()
343 if (DefSU == &ExitSU) in addPhysRegDeps()
998 ExitSU.addPred(Dep); in buildSchedGraph()
1382 else if (SU == &ExitSU) in getGraphNodeLabel()
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| D | PostRASchedulerList.cpp | 489 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) in ReleaseSucc()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 564 SUnit ExitSU; ///< Special node for the region exit. variable
692 SUnit *ExitSU;
725 ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits, SUnit *ExitSU);
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| D | MachinePipeliner.h | 203 RegClassInfo(rci), II_setByPragma(II), Topo(SUnits, &ExitSU) { in SwingSchedulerDAG()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 585 SUnit ExitSU; // Special node for the region exit.
712 SUnit *ExitSU;
734 ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits, SUnit *ExitSU);
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| D | MachineScheduler.h | 258 LIS(C->LIS), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU), in ScheduleDAGMI()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGVLIW.cpp | 132 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) { in releaseSucc()
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| D | ScheduleDAGSDNodes.cpp | 699 if (ExitSU.getNode() != nullptr) in dump()
700 dumpNodeAll(ExitSU); in dump()
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| D | ScheduleDAGFast.cpp | 528 ReleasePredecessors(&ExitSU, CurCycle); in ListScheduleBottomUp()
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| D | ScheduleDAGRRList.cpp | 1599 ReleasePredecessors(&ExitSU); in ListScheduleBottomUp()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGVLIW.cpp | 135 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) { in releaseSucc()
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| D | ScheduleDAGFast.cpp | 536 ReleasePredecessors(&ExitSU, CurCycle); in ListScheduleBottomUp()
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| D | ScheduleDAGRRList.cpp | 1489 ReleasePredecessors(&ExitSU); in ListScheduleBottomUp()
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| /external/llvm/test/CodeGen/X86/ |
| D | misched-new.ll | 58 ; Test that the DAG builder can handle an undef vreg on ExitSU.
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNILPSched.cpp | 311 releasePredecessors(&DAG.ExitSU); in schedule()
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| D | SIMachineScheduler.h | 462 SUnit& getExitSU() { return ExitSU; } in getExitSU()
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| D | AMDGPUSubtarget.cpp | 791 if (&SU != &DAG->ExitSU) { in apply()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIMachineScheduler.h | 454 SUnit& getExitSU() { return ExitSU; }; in getExitSU()
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