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Searched refs:Gather4 (Results 1 – 15 of 15) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DSIIntrinsics.td142 // Gather4 with comparison
150 // Gather4 with offsets
158 // Gather4 with comparison and offsets
DSIDefines.h44 Gather4 = 1 << 25 enumerator
DSIInstrInfo.h320 return MI.getDesc().TSFlags & SIInstrFlags::Gather4; in isGather4()
324 return get(Opcode).TSFlags & SIInstrFlags::Gather4; in isGather4()
DSIInstrFormats.td51 field bits<1> Gather4 = 0;
83 let TSFlags{25} = Gather4;
DSIInstrInfo.td3561 let Gather4 = 1;
/external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/
Dbuilder_mem.h110 void Gather4(const SWR_FORMAT format,
Dbuilder_mem.cpp245 void Builder::Gather4(const SWR_FORMAT format, in Gather4() function in SwrJit::Builder
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td61 field bit Gather4 = 0;
167 let TSFlags{37} = Gather4;
DMIMGInstructions.td35 bit Gather4 = 0;
50 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler", "Gather4",
677 let Gather4 = 1;
681 Gather4 = 1, hasPostISelHook = 0 in {
DSIDefines.h64 Gather4 = UINT64_C(1) << 37, enumerator
DSIInstrInfo.h490 return MI.getDesc().TSFlags & SIInstrFlags::Gather4; in isGather4()
494 return get(Opcode).TSFlags & SIInstrFlags::Gather4; in isGather4()
DSIISelLowering.cpp5386 DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask); in lowerImage()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/
DAMDGPUBaseInfo.h210 bool Gather4; member
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp486 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; in convertMIMGInst()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp2964 (Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : countPopulation(DMask); in validateMIMGDataSize()
3039 if ((Desc.TSFlags & SIInstrFlags::Gather4) == 0) in validateMIMGGatherDMask()