Searched refs:HWREG (Results 1 – 9 of 9) sorted by relevance
88 HWREG(SYS_CTRL_RCGCUART) = (SYS_CTRL_RCGCUART_UART0 | SYS_CTRL_RCGCUART_UART1); in enable_uart_clocks()89 HWREG(SYS_CTRL_SCGCUART) = (SYS_CTRL_SCGCUART_UART0 | SYS_CTRL_SCGCUART_UART1); in enable_uart_clocks()90 HWREG(SYS_CTRL_DCGCUART) = (SYS_CTRL_DCGCUART_UART0 | SYS_CTRL_DCGCUART_UART1); in enable_uart_clocks()92 HWREG(SYS_CTRL_RCGCUART) = SYS_CTRL_RCGCUART_UART0; in enable_uart_clocks()93 HWREG(SYS_CTRL_SCGCUART) = SYS_CTRL_SCGCUART_UART0; in enable_uart_clocks()94 HWREG(SYS_CTRL_DCGCUART) = SYS_CTRL_DCGCUART_UART0; in enable_uart_clocks()108 HWREG(UART0_BASE + UART_O_CC) = 0; in otPlatUartEnable()111 HWREG(IOC_PA1_SEL) = IOC_MUX_OUT_SEL_UART0_TXD; in otPlatUartEnable()112 HWREG(IOC_PA1_OVER) = IOC_OVERRIDE_OE; in otPlatUartEnable()113 HWREG(GPIO_A_BASE + GPIO_O_AFSEL) |= GPIO_PIN_1; in otPlatUartEnable()[all …]
190 HWREG(RFCORE_SFR_RFST) = RFCORE_SFR_RFST_INSTR_FLUSHRX; in enableReceiver()191 HWREG(RFCORE_SFR_RFST) = RFCORE_SFR_RFST_INSTR_FLUSHRX; in enableReceiver()194 HWREG(RFCORE_SFR_RFST) = RFCORE_SFR_RFST_INSTR_RXON; in enableReceiver()205 while (HWREG(RFCORE_XREG_FSMSTAT1) & RFCORE_XREG_FSMSTAT1_TX_ACTIVE) in disableReceiver()209 HWREG(RFCORE_SFR_RFST) = RFCORE_SFR_RFST_INSTR_FLUSHRX; in disableReceiver()210 HWREG(RFCORE_SFR_RFST) = RFCORE_SFR_RFST_INSTR_FLUSHRX; in disableReceiver()212 if (HWREG(RFCORE_XREG_RXENABLE) != 0) in disableReceiver()215 HWREG(RFCORE_SFR_RFST) = RFCORE_SFR_RFST_INSTR_RFOFF; in disableReceiver()236 HWREG(RFCORE_XREG_FREQCTRL) = 11 + (aChannel - 11) * 5; in setChannel()262 HWREG(RFCORE_XREG_TXPOWER) = sTxPowerTable[i].mTxPowerReg; in setTxPower()[all …]
46 HWREG(SOC_ADC_ADCCON1) &= ~(SOC_ADC_ADCCON1_RCTRL1 | SOC_ADC_ADCCON1_RCTRL0); in generateRandom()47 HWREG(SYS_CTRL_RCGCRFC) = SYS_CTRL_RCGCRFC_RFC0; in generateRandom()49 while (HWREG(SYS_CTRL_RCGCRFC) != SYS_CTRL_RCGCRFC_RFC0) in generateRandom()52 frmctrl0 = HWREG(RFCORE_XREG_FRMCTRL0); in generateRandom()53 HWREG(RFCORE_XREG_FRMCTRL0) = RFCORE_XREG_FRMCTRL0_INFINITY_RX; in generateRandom()54 HWREG(RFCORE_SFR_RFST) = RFCORE_SFR_RFST_INSTR_RXON; in generateRandom()56 while (!HWREG(RFCORE_XREG_RSSISTAT) & RFCORE_XREG_RSSISTAT_RSSI_VALID) in generateRandom()66 aOutput[index] |= (HWREG(RFCORE_XREG_RFRND) & RFCORE_XREG_RFRND_IRND); in generateRandom()70 HWREG(RFCORE_SFR_RFST) = RFCORE_SFR_RFST_INSTR_RFOFF; in generateRandom()71 HWREG(RFCORE_XREG_FRMCTRL0) = frmctrl0; in generateRandom()[all …]
186 HWREG(SYS_CTRL_EMUOVR) = 0xFF; in ResetHandler()189 HWREG(SYS_CTRL_CLOCK_CTRL) |= SYS_CTRL_CLOCK_CTRL_AMP_DET; in ResetHandler()190 HWREG(SYS_CTRL_CLOCK_CTRL) = SYS_CTRL_SYSDIV_32MHZ; in ResetHandler()193 HWREG(SYS_CTRL_I_MAP) |= SYS_CTRL_I_MAP_ALTMAP; in ResetHandler()
75 while (HWREG(FLASH_CTRL_FCTL) & FLASH_CTRL_FCTL_BUSY) in otPlatFlashErase()90 while (HWREG(FLASH_CTRL_FCTL) & FLASH_CTRL_FCTL_BUSY) in otPlatFlashWrite()
68 HWREG(NVIC_ST_RELOAD) = kSystemClock / kTicksPerSec; in cc2538AlarmInit()69 HWREG(NVIC_ST_CTRL) = NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_INTEN | NVIC_ST_CTRL_ENABLE; in cc2538AlarmInit()
42 #define HWREG(x) (*((volatile uint32_t *)(x))) macro50 #define HWREG_ARR(reg, idx) HWREG((reg) + ((idx) << 2))
36 HWREG(SYS_CTRL_PWRDBG) = SYS_CTRL_PWRDBG_FORCE_WARM_RESET; in otPlatReset()
1333 def HWREG {