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Searched refs:HalfVT (Results 1 – 21 of 21) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DValueTypes.h298 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT() local
299 if (HalfVT.getSizeInBits() * 2 >= EVTSize) in getHalfSizedIntegerVT()
300 return HalfVT; in getHalfSizedIntegerVT()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.h348 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT() local
349 if (HalfVT.getSizeInBits() * 2 >= EVTSize) in getHalfSizedIntegerVT()
350 return HalfVT; in getHalfSizedIntegerVT()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp1643 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); in LowerUDIVREM64() local
1645 SDValue One = DAG.getConstant(1, DL, HalfVT); in LowerUDIVREM64()
1646 SDValue Zero = DAG.getConstant(0, DL, HalfVT); in LowerUDIVREM64()
1650 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero); in LowerUDIVREM64()
1651 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, One); in LowerUDIVREM64()
1654 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero); in LowerUDIVREM64()
1655 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, One); in LowerUDIVREM64()
1660 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerUDIVREM64()
1694 SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2); in LowerUDIVREM64()
1695 SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc); in LowerUDIVREM64()
[all …]
DSIISelLowering.cpp4984 EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), 2); in lowerBUILD_VECTOR() local
4988 SDValue Lo = DAG.getBuildVector(HalfVT, SL, in lowerBUILD_VECTOR()
4990 SDValue Hi = DAG.getBuildVector(HalfVT, SL, in lowerBUILD_VECTOR()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp1341 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); in LowerUDIVREM64() local
1343 SDValue one = DAG.getConstant(1, DL, HalfVT); in LowerUDIVREM64()
1344 SDValue zero = DAG.getConstant(0, DL, HalfVT); in LowerUDIVREM64()
1348 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero); in LowerUDIVREM64()
1349 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one); in LowerUDIVREM64()
1352 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero); in LowerUDIVREM64()
1353 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one); in LowerUDIVREM64()
1359 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerUDIVREM64()
1371 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo); in LowerUDIVREM64()
1372 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo); in LowerUDIVREM64()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InterleavedAccess.cpp367 MVT HalfVT = scaleVectorType(VT); in interleave8bitStride4() local
385 createUnpackShuffleMask<uint32_t>(HalfVT, MaskLowTemp, true, false); in interleave8bitStride4()
386 createUnpackShuffleMask<uint32_t>(HalfVT, MaskHighTemp, false, false); in interleave8bitStride4()
DX86ISelLowering.cpp8235 EVT HalfVT = in EltsFromConsecutiveLoads() local
8238 EltsFromConsecutiveLoads(HalfVT, Elts.drop_back(HalfNumElems), DL, in EltsFromConsecutiveLoads()
9325 MVT HalfVT = VT.getHalfNumVectorElementsVT(); in getHopForBuildVector() local
9328 SDValue Half = DAG.getNode(HOpcode, SDLoc(BV), HalfVT, V0, V1); in getHopForBuildVector()
10249 MVT HalfVT = ResVT.getHalfNumVectorElementsVT(); in LowerAVXCONCAT_VECTORS() local
10251 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, in LowerAVXCONCAT_VECTORS()
10253 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, in LowerAVXCONCAT_VECTORS()
10338 MVT HalfVT = ResVT.getHalfNumVectorElementsVT(); in LowerCONCAT_VECTORSvXi1() local
10340 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, in LowerCONCAT_VECTORSvXi1()
10342 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, in LowerCONCAT_VECTORSvXi1()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.cpp1014 EVT HalfVT = in SplitInteger() local
1016 SplitInteger(Op, HalfVT, HalfVT, Lo, Hi); in SplitInteger()
DLegalizeVectorTypes.cpp2560 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, in SplitVecOp_TruncateHelper() local
2567 HalfLo = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other}, in SplitVecOp_TruncateHelper()
2569 HalfHi = DAG.getNode(N->getOpcode(), DL, {HalfVT, MVT::Other}, in SplitVecOp_TruncateHelper()
2576 HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec); in SplitVecOp_TruncateHelper()
2577 HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec); in SplitVecOp_TruncateHelper()
DDAGCombiner.cpp4731 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2); in visitANDLike() local
4737 TLI.isNarrowingProfitable(VT, HalfVT) && in visitANDLike()
4738 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) && in visitANDLike()
4739 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) && in visitANDLike()
4740 TLI.isTruncateFree(VT, HalfVT) && in visitANDLike()
4741 TLI.isZExtFree(HalfVT, VT)) { in visitANDLike()
4751 EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout()); in visitANDLike()
4752 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, HalfVT, in visitANDLike()
4755 SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT); in visitANDLike()
4757 SDValue Shift = DAG.getNode(ISD::SRL, SL, HalfVT, Trunc, ShiftK); in visitANDLike()
[all …]
DTargetLowering.cpp1656 EVT HalfVT = Op.getOperand(0).getValueType(); in SimplifyDemandedBits() local
1657 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits(); in SimplifyDemandedBits()
7636 EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext()); in expandVecReduce() local
7637 if (!isOperationLegalOrCustom(BaseOpcode, HalfVT)) in expandVecReduce()
7642 Op = DAG.getNode(BaseOpcode, dl, HalfVT, Lo, Hi); in expandVecReduce()
7643 VT = HalfVT; in expandVecReduce()
DLegalizeIntegerTypes.cpp3535 EVT HalfVT = LHSLow.getValueType() in ExpandIntRes_XMULO() local
3537 SDVTList VTHalfMulO = DAG.getVTList(HalfVT, BitVT); in ExpandIntRes_XMULO()
3540 SDValue HalfZero = DAG.getConstant(0, dl, HalfVT); in ExpandIntRes_XMULO()
DSelectionDAGBuilder.cpp231 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); in getCopyFromParts() local
235 PartVT, HalfVT, V); in getCopyFromParts()
237 RoundParts / 2, PartVT, HalfVT, V); in getCopyFromParts()
239 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
240 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.cpp1161 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), in SplitInteger() local
1163 SplitInteger(Op, HalfVT, HalfVT, Lo, Hi); in SplitInteger()
DDAGCombiner.cpp2971 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2); in visitANDLike() local
2977 TLI.isNarrowingProfitable(VT, HalfVT) && in visitANDLike()
2978 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) && in visitANDLike()
2979 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) && in visitANDLike()
2980 TLI.isTruncateFree(VT, HalfVT) && in visitANDLike()
2981 TLI.isZExtFree(HalfVT, VT)) { in visitANDLike()
2991 EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout()); in visitANDLike()
2992 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, HalfVT, in visitANDLike()
2995 SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT); in visitANDLike()
2997 SDValue Shift = DAG.getNode(ISD::SRL, SL, HalfVT, Trunc, ShiftK); in visitANDLike()
[all …]
DLegalizeVectorTypes.cpp1971 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, in SplitVecOp_TruncateHelper() local
1973 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec); in SplitVecOp_TruncateHelper()
1974 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec); in SplitVecOp_TruncateHelper()
DSelectionDAGBuilder.cpp154 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); in getCopyFromParts() local
158 PartVT, HalfVT, V); in getCopyFromParts()
160 RoundParts / 2, PartVT, HalfVT, V); in getCopyFromParts()
162 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
163 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
DTargetLowering.cpp935 EVT HalfVT = Op.getOperand(0).getValueType(); in SimplifyDemandedBits() local
936 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits(); in SimplifyDemandedBits()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp6914 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(), in LowerAVXCONCAT_VECTORS() local
6919 concat128BitVectors(V1, V2, HalfVT, NumElems / 2, DAG, dl), in LowerAVXCONCAT_VECTORS()
6920 concat128BitVectors(V3, V4, HalfVT, NumElems / 2, DAG, dl), ResVT, in LowerAVXCONCAT_VECTORS()
6956 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(), in LowerCONCAT_VECTORSvXi1() local
6961 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops); in LowerCONCAT_VECTORSvXi1()
6965 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops); in LowerCONCAT_VECTORSvXi1()
10869 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(), HalfNumElts); in lowerVectorShuffleWithUndefHalf() local
10880 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V1, in lowerVectorShuffleWithUndefHalf()
10890 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V1, in lowerVectorShuffleWithUndefHalf()
10963 return DAG.getUNDEF(HalfVT); in lowerVectorShuffleWithUndefHalf()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp8974 auto *HalfVT = cast<VectorType>(HalfV->getType()); in areExtractShuffleVectors() local
8975 return FullVT->getBitWidth() == 2 * HalfVT->getBitWidth(); in areExtractShuffleVectors()
8980 auto *HalfVT = cast<VectorType>(HalfV->getType()); in areExtractShuffleVectors() local
8981 return FullVT->getNumElements() == 2 * HalfVT->getNumElements(); in areExtractShuffleVectors()
11469 EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext()); in splitStores() local
11470 unsigned NumElts = HalfVT.getVectorNumElements(); in splitStores()
11471 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, in splitStores()
11473 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, in splitStores()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp8792 EVT HalfVT = in split16BStores() local
8794 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, in split16BStores()
8796 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, in split16BStores()