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Searched refs:HasLaneSize (Results 1 – 9 of 9) sorted by relevance

/external/vixl/src/aarch64/
Dregisters-aarch64.h117 bool HasLaneSize() const { return lane_size_ != kEncodedUnknownSize; } in HasLaneSize() function
143 VIXL_ASSERT(HasLaneSize()); in GetLaneSizeInBytesLog2()
148 if (HasSize() && HasLaneSize()) { in GetLanes()
224 bool IsVector() const { return HasLaneSize() && (size_ != lane_size_); } in IsVector()
225 bool IsScalar() const { return HasLaneSize() && (size_ == lane_size_); } in IsScalar()
624 VIXL_ASSERT(other.HasLaneSize()); in WithSameLaneSizeAs()
641 return IsValidPRegister() && !HasLaneSize() && IsUnqualified(); in IsValid()
693 return IsValidPRegister() && HasLaneSize() && IsUnqualified(); in IsValid()
702 VIXL_ASSERT(HasLaneSize()); in GetLaneSizeInBits()
707 VIXL_ASSERT(HasLaneSize()); in GetLaneSizeInBytes()
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Dregisters-aarch64.cc39 if (HasLaneSize()) { in GetArchitecturalName()
44 if (HasLaneSize()) { in GetArchitecturalName()
Doperands-aarch64.h647 VIXL_ASSERT(base_.HasLaneSize()); in GetVectorBase()
658 VIXL_ASSERT(regoffset_.HasLaneSize()); in GetVectorOffset()
Dassembler-aarch64.h6992 VIXL_ASSERT(!pg.HasLaneSize()); in PgLow8()
7000 VIXL_ASSERT(!pg.HasLaneSize()); in Pg()
7494 VIXL_ASSERT(rd.HasLaneSize()); in SVESize()
Dassembler-sve-aarch64.cc3283 VIXL_ASSERT(!pg.HasLaneSize()); in movprfx()
6095 if (pg.HasLaneSize()) VIXL_ASSERT(AreSameFormat(pg, pn)); in cntp()
6516 VIXL_ASSERT((!pd.HasLaneSize() && !pn.HasLaneSize()) || in mov()
Dmacro-assembler-aarch64.h5577 VIXL_ASSERT(!pd.HasLaneSize() || pd.IsLaneSizeB()); in Rdffr()
6362 VIXL_ASSERT(!pn.HasLaneSize() || pn.IsLaneSizeB()); in Wrffr()
Dassembler-aarch64.cc1972 VIXL_ASSERT(vt.HasSize() && vt.HasLaneSize()); in LoadStoreStructVerify()
/external/vixl/test/aarch64/
Dtest-utils-aarch64.h411 VIXL_ASSERT(reg.HasLaneSize()); in EqualSVE()
438 VIXL_ASSERT(reg.HasLaneSize()); in EqualSVE()
460 if (!result.HasLaneSize()) { in EqualSVE()
Dtest-utils-aarch64.cc390 VIXL_ASSERT(reg.HasLaneSize()); in EqualSVELane()