1 /* 2 * Copyright (c) 2015 - 2020, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <common/debug.h> 9 #include <lib/mmio.h> 10 11 #include <platform_def.h> 12 #include <timer_sync.h> 13 14 /******************************************************************************* 15 * Defines related to time sync and satelite timers 16 ******************************************************************************/ 17 #define TIME_SYNC_WR_ENA ((uint32_t)0xACCE55 << 8) 18 #define IHOST_STA_TMR_CTRL 0x1800 19 #define IHOST_SAT_TMR_INC_L 0x1814 20 #define IHOST_SAT_TMR_INC_H 0x1818 21 22 #define SAT_TMR_CYCLE_DELAY 2 23 #define SAT_TMR_32BIT_WRAP_VAL (BIT_64(32) - SAT_TMR_CYCLE_DELAY) 24 ihost_enable_satellite_timer(unsigned int cluster_id)25void ihost_enable_satellite_timer(unsigned int cluster_id) 26 { 27 uintptr_t ihost_base; 28 uint32_t time_lx, time_h; 29 uintptr_t ihost_enable; 30 31 VERBOSE("Program iHost%u satellite timer\n", cluster_id); 32 ihost_base = IHOST0_BASE + cluster_id * IHOST_ADDR_SPACE; 33 34 /* this read starts the satellite timer counting from 0 */ 35 ihost_enable = CENTRAL_TIMER_GET_IHOST_ENA_BASE + cluster_id * 4; 36 time_lx = mmio_read_32(ihost_enable); 37 38 /* 39 * Increment the satellite timer by the central timer plus 2 40 * to accommodate for a 1 cycle delay through NOC 41 * plus counter starting from 0. 42 */ 43 mmio_write_32(ihost_base + IHOST_SAT_TMR_INC_L, 44 time_lx + SAT_TMR_CYCLE_DELAY); 45 46 /* 47 * Read the latched upper data, if lx will wrap by adding 2 to it 48 * we need to handle the wrap 49 */ 50 time_h = mmio_read_32(CENTRAL_TIMER_GET_H); 51 if (time_lx >= SAT_TMR_32BIT_WRAP_VAL) 52 mmio_write_32(ihost_base + IHOST_SAT_TMR_INC_H, time_h + 1); 53 else 54 mmio_write_32(ihost_base + IHOST_SAT_TMR_INC_H, time_h); 55 } 56 brcm_timer_sync_init(void)57void brcm_timer_sync_init(void) 58 { 59 unsigned int cluster_id; 60 61 /* Get the Time Sync module out of reset */ 62 mmio_setbits_32(CDRU_MISC_RESET_CONTROL, 63 BIT(CDRU_MISC_RESET_CONTROL_TS_RESET_N)); 64 65 /* Deassert the Central Timer TIMER_EN signal for all module */ 66 mmio_write_32(CENTRAL_TIMER_SAT_TMR_ENA, TIME_SYNC_WR_ENA); 67 68 /* enables/programs iHost0 satellite timer*/ 69 cluster_id = MPIDR_AFFLVL1_VAL(read_mpidr()); 70 ihost_enable_satellite_timer(cluster_id); 71 } 72