Searched refs:InitReg (Results 1 – 5 of 5) sorted by relevance
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ModuloSchedule.cpp | 1268 Register phi(Register LoopReg, Optional<Register> InitReg = {},
1449 Register KernelRewriter::phi(Register LoopReg, Optional<Register> InitReg, in phi() argument
1452 if (InitReg.hasValue()) { in phi()
1453 auto I = Phis.find({LoopReg, InitReg.getValue()}); in phi()
1468 if (!InitReg.hasValue()) in phi()
1474 MI->getOperand(1).setReg(InitReg.getValue()); in phi()
1475 Phis.insert({{LoopReg, InitReg.getValue()}, R}); in phi()
1476 MRI.constrainRegClass(R, MRI.getRegClass(InitReg.getValue())); in phi()
1485 if (InitReg.hasValue()) in phi()
1486 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); in phi()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDILCFGStructurizer.cpp | 1320 Register InitReg = in improveSimpleJumpintoIf() local
1322 insertCondBranchBefore(LandBlk, I, R600::IF_PREDICATE_SET, InitReg, in improveSimpleJumpintoIf()
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| D | AMDGPURegisterBankInfo.cpp | 763 Register InitReg = B.buildUndef(ResTy).getReg(0); in executeInWaterfallLoop() local
765 InitResultRegs.push_back(InitReg); in executeInWaterfallLoop()
768 MRI.setRegBank(InitReg, *DefBank); in executeInWaterfallLoop()
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| D | SIISelLowering.cpp | 3177 unsigned InitReg, in emitLoadM0FromVGPRLoop() argument
3196 .addReg(InitReg) in emitLoadM0FromVGPRLoop()
3443 Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in emitIndirectSrc() local
3445 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg); in emitIndirectSrc()
3447 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, in emitIndirectSrc()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDILCFGStructurizer.cpp | 1358 unsigned InitReg = in improveSimpleJumpintoIf() local
1360 insertCondBranchBefore(LandBlk, I, AMDGPU::IF_PREDICATE_SET, InitReg, in improveSimpleJumpintoIf()
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