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Searched refs:IsD (Results 1 – 5 of 5) sorted by relevance

/external/vixl/src/aarch64/
Dregisters-aarch64.h314 bool IsD() const { return IsVRegister() && Is64Bits(); } in IsD() function
323 bool Is1D() const { return IsD() && IsScalar(); } in Is1D()
327 bool Is8B() const { return IsD() && IsLaneSizeB(); } in Is8B()
330 bool Is4H() const { return IsD() && IsLaneSizeH(); } in Is4H()
332 bool Is2S() const { return IsD() && IsLaneSizeS(); } in Is2S()
Dassembler-aarch64.cc2428 V(saddl, NEON_SADDL, vn.IsVector() && vn.IsD()) \
2430 V(sabal, NEON_SABAL, vn.IsVector() && vn.IsD()) \
2432 V(uabal, NEON_UABAL, vn.IsVector() && vn.IsD()) \
2434 V(sabdl, NEON_SABDL, vn.IsVector() && vn.IsD()) \
2436 V(uabdl, NEON_UABDL, vn.IsVector() && vn.IsD()) \
2438 V(smlal, NEON_SMLAL, vn.IsVector() && vn.IsD()) \
2440 V(umlal, NEON_UMLAL, vn.IsVector() && vn.IsD()) \
2442 V(smlsl, NEON_SMLSL, vn.IsVector() && vn.IsD()) \
2444 V(umlsl, NEON_UMLSL, vn.IsVector() && vn.IsD()) \
2446 V(smull, NEON_SMULL, vn.IsVector() && vn.IsD()) \
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Dmacro-assembler-aarch64.h1923 if (vt.IsD()) { in Ldr()
/external/vixl/src/aarch32/
Dinstructions-aarch32.h116 bool IsD() const { return GetType() == kDRegister; } in IsD() function
118 bool IsVRegister() const { return IsS() || IsD() || IsQ(); } in IsVRegister()
119 bool IsFPRegister() const { return IsS() || IsD(); } in IsFPRegister()
Dmacro-assembler-aarch32.h10503 VIXL_ASSERT(rd.IsS() || rd.IsD()); in Vabs()
10513 VIXL_ASSERT(rd.IsS() || rd.IsD()); in Vadd()
10524 VIXL_ASSERT(rd.IsS() || rd.IsD()); in Vcmp()
10534 VIXL_ASSERT(rd.IsS() || rd.IsD()); in Vcmpe()
10544 VIXL_ASSERT(rd.IsS() || rd.IsD()); in Vdiv()
10555 VIXL_ASSERT(rd.IsS() || rd.IsD()); in Vfma()
10566 VIXL_ASSERT(rd.IsS() || rd.IsD()); in Vfms()
10577 VIXL_ASSERT(rd.IsS() || rd.IsD()); in Vfnma()
10590 VIXL_ASSERT(rd.IsS() || rd.IsD()); in Vfnms()
10603 VIXL_ASSERT(rd.IsS() || rd.IsD()); in Vmaxnm()
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