1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef JUNO_TZMP1_DEF_H 8 #define JUNO_TZMP1_DEF_H 9 10 /* 11 * Public memory regions for both protected and non-protected mode 12 * 13 * OPTEE shared memory 0xFEE00000 - 0xFEFFFFFF 14 */ 15 #define JUNO_AP_TZC_SHARE_DRAM1_SIZE ULL(0x02000000) 16 #define JUNO_AP_TZC_SHARE_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ 17 JUNO_AP_TZC_SHARE_DRAM1_SIZE) 18 #define JUNO_AP_TZC_SHARE_DRAM1_END (ARM_AP_TZC_DRAM1_BASE - 1) 19 20 /* ARM_MEDIA_FEATURES for MEDIA GPU Protect Mode Test */ 21 #define JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE 8 /* GPU/DPU protected, VPU outbuf */ 22 #define JUNO_TZC400_NSAID_FPGA_VIDEO_PROTECTED 7 /* VPU protected */ 23 #define JUNO_TZC400_NSAID_FPGA_VIDEO_PRIVATE 10 /* VPU private (firmware) */ 24 25 #define JUNO_VPU_TZC_PRIV_DRAM1_SIZE ULL(0x02000000) 26 #define JUNO_VPU_TZC_PRIV_DRAM1_BASE (JUNO_AP_TZC_SHARE_DRAM1_BASE - \ 27 JUNO_VPU_TZC_PRIV_DRAM1_SIZE) 28 #define JUNO_VPU_TZC_PRIV_DRAM1_END (JUNO_AP_TZC_SHARE_DRAM1_BASE - 1) 29 30 /* Video input protected buffer follows upper item */ 31 #define JUNO_VPU_TZC_PROT_DRAM1_SIZE ULL(0x06000000) 32 #define JUNO_VPU_TZC_PROT_DRAM1_BASE (JUNO_VPU_TZC_PRIV_DRAM1_BASE - \ 33 JUNO_VPU_TZC_PROT_DRAM1_SIZE) 34 #define JUNO_VPU_TZC_PROT_DRAM1_END (JUNO_VPU_TZC_PRIV_DRAM1_BASE - 1) 35 36 /* Video, graphics and display shares same NSAID and same protected buffer */ 37 #define JUNO_MEDIA_TZC_PROT_DRAM1_SIZE ULL(0x0e000000) 38 #define JUNO_MEDIA_TZC_PROT_DRAM1_BASE (JUNO_VPU_TZC_PROT_DRAM1_BASE - \ 39 JUNO_MEDIA_TZC_PROT_DRAM1_SIZE) 40 #define JUNO_MEDIA_TZC_PROT_DRAM1_END (JUNO_VPU_TZC_PROT_DRAM1_BASE - 1) 41 42 /* Rest of DRAM1 are Non-Secure public buffer */ 43 #define JUNO_NS_DRAM1_PT1_BASE ARM_DRAM1_BASE 44 #define JUNO_NS_DRAM1_PT1_END (JUNO_MEDIA_TZC_PROT_DRAM1_BASE - 1) 45 #define JUNO_NS_DRAM1_PT1_SIZE (JUNO_NS_DRAM1_PT1_END - \ 46 JUNO_NS_DRAM1_PT1_BASE + 1) 47 48 /* TZC filter flags */ 49 #define JUNO_MEDIA_TZC_NS_DEV_ACCESS (PLAT_ARM_TZC_NS_DEV_ACCESS | \ 50 TZC_REGION_ACCESS_RD(JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE)) 51 52 /* VPU / GPU /DPU protected access */ 53 #define JUNO_MEDIA_TZC_PROT_ACCESS \ 54 (TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE) | \ 55 TZC_REGION_ACCESS_WR(TZC400_NSAID_AP)) 56 57 #define JUNO_VPU_TZC_PROT_ACCESS \ 58 (TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_VIDEO_PROTECTED)) 59 60 #define JUNO_VPU_TZC_PRIV_ACCESS \ 61 (TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_VIDEO_PRIVATE)) 62 63 /******************************************************************************* 64 * Mali-DP650 related constants 65 ******************************************************************************/ 66 /* Base address of DP650 */ 67 #define DP650_BASE 0x6f200000 68 /* offset to PROT_NSAID register */ 69 #define DP650_PROT_NSAID_OFFSET 0x10004 70 /* config to PROT_NSAID register */ 71 #define DP650_PROT_NSAID_CONFIG 0x08008888 72 73 /******************************************************************************* 74 * Mali-V550 related constants 75 ******************************************************************************/ 76 /* Base address of V550 */ 77 #define V550_BASE 0x6f030000 78 /* offset to PROTCTRL register */ 79 #define V550_PROTCTRL_OFFSET 0x0040 80 /* config to PROTCTRL register */ 81 #define V550_PROTCTRL_CONFIG 0xa8700000 82 83 #endif /* JUNO_TZMP1_DEF_H */ 84