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Searched refs:LDLARB (Results 1 – 16 of 16) sorted by relevance

/external/vixl/src/aarch64/
Dcpu-features-auditor-aarch64.cc602 case LDLARB: in VisitLoadStoreExclusive()
Dconstants-aarch64.h1234 LDLARB = LoadStoreExclusiveFixed | 0x00C00000, enumerator
Dassembler-aarch64.cc1623 Emit(LDLARB | Rs_mask | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister())); in ldlarb()
Dsimulator-aarch64.cc4631 case LDLARB: in VisitLoadStoreExclusive()
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1117 case AArch64::LDLARB: in DecodeExclusiveLdStInstruction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1323 case AArch64::LDLARB: in DecodeExclusiveLdStInstruction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedThunderX2T99.td1770 (instrs LDLARB, LDLARH, LDLARW, LDLARX)>;
DAArch64InstrInfo.td3288 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenMCCodeEmitter.inc2438 UINT64_C(148864000), // LDLARB
11995 case AArch64::LDLARB:
18367 CEFBS_HasLOR, // LDLARB = 2425
DAArch64GenAsmWriter.inc3387 2255013590U, // LDLARB
8777 28U, // LDLARB
DAArch64GenAsmWriter1.inc4384 415436032U, // LDLARB
9774 56U, // LDLARB
DAArch64GenInstrInfo.inc2440 LDLARB = 2425,
9324 …deledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2425 = LDLARB
DAArch64GenAsmMatcher.inc16049 …{ 2517 /* ldlarb */, AArch64::LDLARB, Convert__Reg1_0__GPR64sp01_2, AMFBS_HasLOR, { MCK_GPR32, MCK…
23422 …{ 2517 /* ldlarb */, AArch64::LDLARB, Convert__Reg1_0__GPR64sp01_2, AMFBS_HasLOR, { MCK_GPR32, MCK…
DAArch64GenDisassemblerTables.inc8829 /* 41408 */ MCD::OPC_Decode, 249, 18, 168, 1, // Opcode: LDLARB
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md1222 ### LDLARB ### subsection
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2479 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;