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Searched refs:LSU (Results 1 – 25 of 29) sorted by relevance

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/external/mesa3d/src/mesa/sparc/
Dxform.S77 1: ld [%g1 + 0x00], %f0 ! LSU Group
79 ld [%g1 + 0x00], %f8 ! LSU Group
88 st %f1, [%g2 + 0x00] ! LSU
91 st %f2, [%g2 + 0x04] ! LSU
94 st %f3, [%g2 + 0x08] ! LSU
97 st %f4, [%g2 + 0x0c] ! LSU
99 st %f9, [%g2 + 0x10] ! LSU
101 st %f10, [%g2 + 0x14] ! LSU
103 st %f11, [%g2 + 0x18] ! LSU
105 st %f12, [%g2 + 0x1c] ! LSU
[all …]
Dsparc_clip.S98 1: ld [%i0 + 0x0c], %f3 ! LSU Group
99 ld [%i0 + 0x0c], %g5 ! LSU Group
100 ld [%i0 + 0x08], %g4 ! LSU Group
107 ld [%i0 + 0x04], %g4 ! LSU Group
112 ld [%i0 + 0x00], %g4 ! LSU Group
118 ldub [%g1 + %g3], %g3 ! LSU Group
121 stb %g3, [%i2] ! LSU
124 st %g0, [%i5 + 0x00] ! LSU
127 st %g0, [%i5 + 0x04] ! LSU
129 st %g0, [%i5 + 0x08] ! LSU
[all …]
Dnorm.S138 ld [%o3], %f13 ! LSU
247 ld [%o3], %f13 ! LSU
306 st %f3, [%g3 + 0x00] ! LSU
308 st %f5, [%g3 + 0x04] ! LSU
310 st %f7, [%g3 + 0x08] ! LSU
371 st %f3, [%g3 + 0x00] ! LSU
373 st %f5, [%g3 + 0x04] ! LSU
375 st %f7, [%g3 + 0x08] ! LSU
413 st %f3, [%g3 + 0x00] ! LSU
415 st %f5, [%g3 + 0x04] ! LSU
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZScheduleZEC12.td83 def : WriteRes<LSU, [ZEC12_LSUnit]>;
88 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
122 def : InstRW<[WLat1, LSU, NormalGr], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
123 def : InstRW<[WLat1, LSU, NormalGr], (instregex "(Call)?B(R)?(Asm.*)?$")>;
125 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BRCTH$")>;
126 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BCT(G)?(R)?$")>;
127 def : InstRW<[WLat1, FXU3, LSU, GroupAlone2],
132 def : InstRW<[WLat1, FXU, LSU, GroupAlone],
146 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
154 def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "(Call)?BRASL$")>;
[all …]
DSystemZScheduleZ196.td82 def : WriteRes<LSU, [Z196_LSUnit]>;
87 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z196_LSUnit]>;
116 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
117 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?J(G)?(Asm.*)?$")>;
118 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
119 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?B(R)?(Asm.*)?$")>;
120 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BRCT(G|H)?$")>;
121 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BCT(G)?(R)?$")>;
122 def : InstRW<[WLat1, FXU3, LSU, GroupAlone2],
126 def : InstRW<[WLat1, FXU, LSU, GroupAlone],
[all …]
DSystemZScheduleZ15.td88 def : WriteRes<LSU, [Z15_LSUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z15_LSUnit]>;
140 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "BI(C)?(Asm.*)?$")>;
163 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
184 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;
185 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MVI(Y)?$")>;
199 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
200 def : InstRW<[LSULatency, LSULatency, LSU, NormalGr], (instregex "LCBB$")>;
201 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
202 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;
[all …]
DSystemZScheduleZ13.td88 def : WriteRes<LSU, [Z13_LSUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z13_LSUnit]>;
162 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
183 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;
184 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MVI(Y)?$")>;
197 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
198 def : InstRW<[LSULatency, LSULatency, LSU, NormalGr], (instregex "LCBB$")>;
199 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
200 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;
210 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LZR(F|G)$")>;
[all …]
DSystemZScheduleZ14.td88 def : WriteRes<LSU, [Z14_LSUnit]>;
98 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z14_LSUnit]>;
140 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "BI(C)?(Asm.*)?$")>;
163 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
184 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;
185 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MVI(Y)?$")>;
198 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
199 def : InstRW<[LSULatency, LSULatency, LSU, NormalGr], (instregex "LCBB$")>;
200 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
201 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;
[all …]
DSystemZSchedule.td22 // A SchedWrite added to other SchedWrites to make LSU latency parameterizable.
29 def "WLat"#L#"LSU" : WriteSequence<[!cast<SchedWrite>("WLat"#L),
43 def "LSU"#Num : SchedWrite;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/HardwareUnits/
DScheduler.cpp55 LSUnit::Status LSS = LSU.isAvailable(IR); in isAvailable()
87 LSU.onInstructionIssued(IR); in issueInstructionImpl()
88 const MemoryGroup &Group = LSU.getGroup(IS->getLSUTokenID()); in issueInstructionImpl()
95 LSU.onInstructionExecuted(IR); in issueInstructionImpl()
106 HasDependentUsers |= Inst.isMemOp() && LSU.hasDependentUsers(IR); in issueInstruction()
135 if (IS.isMemOp() && !LSU.isReady(IR)) { in promoteToReadySet()
172 if (IS.isMemOp() && LSU.isWaiting(IR)) { in promoteToPendingSet()
233 LSU.onInstructionExecuted(IR); in updateIssuedSet()
256 if (IS.isMemOp() && LSU.isPending(IR)) in analyzeDataDependencies()
268 LSU.cycleEvent(); in cycleEvent()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/
DContext.cpp37 auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize, in createDefaultPipeline() local
39 auto HWS = std::make_unique<Scheduler>(SM, *LSU); in createDefaultPipeline()
47 auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU); in createDefaultPipeline()
52 addHardwareUnit(std::move(LSU)); in createDefaultPipeline()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MCA/Stages/
DRetireStage.h31 LSUnitBase &LSU; variable
38 : Stage(), RCU(R), PRF(F), LSU(LS) {} in RetireStage()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MCA/HardwareUnits/
DScheduler.h71 LSUnitBase &LSU; variable
167 : LSU(Lsu), Resources(std::move(RM)), BusyResourceUnits(0), in Scheduler()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/Stages/
DRetireStage.cpp57 LSU.onInstructionRetired(IR); in notifyInstructionRetired()
/external/llvm/lib/Target/PowerPC/
DPPCScheduleP7.td46 // Each LSU pipeline can also execute FX add and logical instructions.
47 // Each LSU pipeline can complete a load or store in one cycle.
49 // Each store is broken into two parts, AGEN goes to the LSU while a
DPPCScheduleP8.td28 // 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
250 // op is issued to the LSU, and the data op (register fetch) is issued
387 // to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
DPPCScheduleE500mc.td26 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
36 def E500_LSU_0 : FuncUnit; // LSU pipeline
DPPCScheduleE5500.td27 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
39 def E5500_LSU_0 : FuncUnit; // LSU pipeline
DPPCInstrInfo.td2159 /// that they will fill slots (which could cause the load of a LSU reject to
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCScheduleP7.td45 // Each LSU pipeline can also execute FX add and logical instructions.
46 // Each LSU pipeline can complete a load or store in one cycle.
48 // Each store is broken into two parts, AGEN goes to the LSU while a
DPPCScheduleP8.td27 // 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
257 // op is issued to the LSU, and the data op (register fetch) is issued
394 // to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
DPPCScheduleE500.td25 // 6 pipelined execution units: SU0, SU1, BU, LSU, MU.
31 def E500_LSU_0 : FuncUnit; // LSU pipeline
DPPCScheduleE500mc.td25 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
35 def E500mc_LSU_0 : FuncUnit; // LSU pipeline
DPPCScheduleE5500.td26 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
38 def E5500_LSU_0 : FuncUnit; // LSU pipeline
/external/cldr/tools/cldr-code/src/main/resources/org/unicode/cldr/util/data/external/
DsubdivisionData.txt128 AO-LSU Lunda Sul

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