| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonShuffler.h | 82 unsigned Lanes; variable
88 void setLanes(unsigned l) { Lanes = l; } in setLanes()
99 unsigned getLanes() const { return Lanes; } in getLanes()
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| D | HexagonShuffler.cpp | 169 unsigned Lanes; member
173 static unsigned makeAllBits(unsigned startBit, unsigned Lanes) in makeAllBits() argument
175 for (unsigned i = 1; i < Lanes; ++i) in makeAllBits()
188 unsigned allBits = makeAllBits(b, hvxInsts[startIdx].Lanes); in checkHVXPipes()
601 inst.Lanes = I->CVI.getLanes(); in check()
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonShuffler.h | 74 unsigned Lanes; variable
80 void setLanes(unsigned l) { Lanes = l; }; in setLanes()
90 unsigned getLanes() const { return (Lanes); }; in getLanes()
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| /external/rust/crates/ppv-lite86/src/ |
| D | types.rs | 209 pub trait MultiLane<Lanes> {
211 fn to_lanes(self) -> Lanes; in to_lanes() argument
213 fn from_lanes(lanes: Lanes) -> Self; in from_lanes()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | MVETailPredication.cpp | 284 unsigned Lanes = cast<VectorType>(Insert->getType())->getNumElements(); in isTailPredicate() local
287 if (!match(InLoop, m_Add(m_Instruction(LHS), m_SpecificInt(Lanes)))) in isTailPredicate()
307 unsigned Lanes = VecTy->getNumElements(); in IsPredicatedVectorLoop() local
312 if (Lanes * ElementWidth > MaxWidth || Lanes == MaxWidth) in IsPredicatedVectorLoop()
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| /external/arm-trusted-firmware/docs/plat/ |
| D | ls1043a.rst | 29 * PCIe2 (Lanes C) to mini-PCIe slot
30 * PCIe3 (Lanes D) to PCIe slot
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIMachineFunctionInfo.cpp | 335 if (!Spill.Lanes.empty()) in allocateVGPRSpillToAGPR()
340 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
382 Spill.Lanes[I] = *NextSpillReg++; in allocateVGPRSpillToAGPR()
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| D | SIMachineFunctionInfo.h | 454 SmallVector<MCPhysReg, 32> Lanes;
512 : I->second.Lanes[Lane];
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| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsAArch64.td | 160 // Vector Add Across Lanes
165 // Vector Long Add Across Lanes
256 // Vector Max Across Lanes
272 // Vector Min Across Lanes
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | IntrinsicsAArch64.td | 177 // Vector Add Across Lanes
182 // Vector Long Add Across Lanes
273 // Vector Max Across Lanes
289 // Vector Min Across Lanes
|
| /external/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 1995 LaneBitmask Lanes = SubRangeJoin ? 1 : TRI->getSubRegIndexLaneMask(SubIdx); in analyzeValue() local
1996 V.ValidLanes = V.WriteLanes = Lanes; in analyzeValue()
2297 LaneBitmask Lanes) const { in usesLanes()
2305 if (Lanes & TRI->getSubRegIndexLaneMask( in usesLanes()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 1313 const size_t Lanes = Op.getNumOperands(); in LowerBUILD_VECTOR() local
1382 for (size_t I = 0; I < Lanes; ++I) { in LowerBUILD_VECTOR()
1460 for (size_t I = 0; I < Lanes; ++I) { in LowerBUILD_VECTOR()
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | detect-dead-lanes.mir | 382 # Lanes are rotate between sub0, sub2, sub3 so only sub1 should be dead/undef.
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 2537 LaneBitmask Lanes = SubRangeJoin ? LaneBitmask::getLane(0) in analyzeValue() local
2539 V.ValidLanes = V.WriteLanes = Lanes; in analyzeValue()
2866 LaneBitmask Lanes) const { in usesLanes()
2875 if ((Lanes & TRI->getSubRegIndexLaneMask(S)).any()) in usesLanes()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Vectorize/ |
| D | LoopVectorize.cpp | 1984 unsigned Lanes = in buildScalarSteps() local
1989 for (unsigned Lane = 0; Lane < Lanes; ++Lane) { in buildScalarSteps()
4170 unsigned Lanes = Cost->isUniformAfterVectorization(P, VF) ? 1 : VF; in widenPHIInstruction() local
4174 for (unsigned Lane = 0; Lane < Lanes; ++Lane) { in widenPHIInstruction()
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| D | SLPVectorizer.cpp | 1209 for (unsigned Lane = 0, Lanes = getNumLanes(); Lane != Lanes; ++Lane) in getVL() local
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 10803 SmallVector<int, 4> Lanes((unsigned)NumLanes, -1); in lowerVectorShuffleByMerging128BitLanes() local
10811 if (Lanes[j] < 0) { in lowerVectorShuffleByMerging128BitLanes()
10813 Lanes[j] = Mask[i] / LaneSize; in lowerVectorShuffleByMerging128BitLanes()
10814 } else if (Lanes[j] != Mask[i] / LaneSize) { in lowerVectorShuffleByMerging128BitLanes()
10834 if (Lanes[i] >= 0) { in lowerVectorShuffleByMerging128BitLanes()
10835 LaneMask[2 * i + 0] = 2*Lanes[i] + 0; in lowerVectorShuffleByMerging128BitLanes()
10836 LaneMask[2 * i + 1] = 2*Lanes[i] + 1; in lowerVectorShuffleByMerging128BitLanes()
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| /external/cldr/tools/cldr-code/src/main/resources/org/unicode/cldr/util/data/external/ |
| D | 2013-1_UNLOCODE_CodeListPart3.csv | 13330 ,"US","XL4","Cross Lanes","Cross Lanes","WV","--3--6--","RL","1207",,"3825N 08147W",
|