| /external/google-breakpad/src/common/android/include/asm-mips/ |
| D | asm.h | 66 #define MOVN(rd, rs, rt) .set push; .set reorder; beqz rt, 9f; move rd, rs; .set pop; 9: macro
71 #define MOVN(rd, rs, rt) .set push; .set noreorder; bnezl rt, 9f; move rd, rs; .set pop; … macro
76 #define MOVN(rd, rs, rt) movn rd, rs, rt macro
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| /external/llvm/test/MC/AArch64/ |
| D | arm64-aliases.s | 179 ; Two 32-bit immediates are encodable by both MOVN and MOVZ, make sure the MOV
196 ; overlaps with MOVZ or MOVN if the repeat-width is the whole register. In
197 ; both cases MOVZ/MOVN are preferred.
222 ; 0xffff is interesting because there are exceptions in the MOVN rules for
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 311 unsigned LL, SC, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOpSubword() local
322 MOVN = Mips::MOVN_I_MM; in expandAtomicBinOpSubword()
334 MOVN = Mips::MOVN_I_I; in expandAtomicBinOpSubword()
460 unsigned MOVIncr = IsMax ? MOVN : MOVZ; in expandAtomicBinOpSubword()
586 unsigned LL, SC, ZERO, BEQ, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOp() local
596 MOVN = Mips::MOVN_I_MM; in expandAtomicBinOp()
611 MOVN = Mips::MOVN_I_I; in expandAtomicBinOp()
626 MOVN = Mips::MOVN_I64_I64; in expandAtomicBinOp()
746 unsigned MOVIncr = IsMax ? MOVN : MOVZ; in expandAtomicBinOp()
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| /external/llvm/test/CodeGen/AArch64/ |
| D | movw-consts.ll | 52 ; A 32-bit MOVN can generate some 64-bit patterns that a 64-bit one
121 ; Mustn't MOVN w0 here.
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| D | arm64-movi.ll | 76 ; Tests for MOVN with MOVK.
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64Schedule.td | 20 def WriteImm : SchedWrite; // MOVN, MOVZ
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| D | AArch64SchedCyclone.td | 130 // MOVN,MOVZ,MOVK
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| D | AArch64InstrInfo.td | 1026 defm MOVN : MoveImmediate<0b00, "movn">;
1090 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
1091 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
1093 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
1094 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
1095 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
1096 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
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| D | AArch64SchedFalkorDetails.td | 1234 def : InstRW<[FalkorWr_1XYZB_0cyc], (instregex "^MOVN(W|X)i$")>; // imm fwd
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64Schedule.td | 21 def WriteImm : SchedWrite; // MOVN, MOVZ
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| D | AArch64SchedCyclone.td | 129 // MOVN,MOVZ,MOVK
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| D | AArch64InstrInfo.td | 443 defm MOVN : MoveImmediate<0b00, "movn">;
507 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
508 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
510 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
511 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
512 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
513 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
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| /external/pcre/src/sljit/ |
| D | sljitNativeARM_64.c | 111 #define MOVN 0x92800000 macro
518 return push_inst(compiler, MOVN | RD(dst) | (((sljit_ins)~imm & 0xffff) << 5)); in load_immediate()
524 return push_inst(compiler, (MOVN ^ W_OP) | RD(dst) | (((sljit_ins)~imm & 0xffff) << 5)); in load_immediate()
526 …return push_inst(compiler, (MOVN ^ W_OP) | RD(dst) | (((sljit_ins)~imm & 0xffff0000u) >> (16 - 5))… in load_immediate()
542 …return push_inst(compiler, MOVN | RD(dst) | (((sljit_ins)~imm & 0xffff0000u) >> (16 - 5)) | (1 << … in load_immediate()
544 FAIL_IF(push_inst(compiler, MOVN | RD(dst) | (((sljit_ins)~imm & 0xffff) << 5))); in load_immediate()
571 FAIL_IF(push_inst(compiler, MOVN | RD(dst) | (((sljit_ins)simm & 0xffff) << 5) | (i << 21))); in load_immediate()
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| D | sljitNativeMIPS_common.c | 292 #define MOVN (HI(0) | LO(11)) macro
3318 ins = MOVN | TA(EQUAL_FLAG); in sljit_emit_cmov()
3325 ins = MOVN | TA(OTHER_FLAG); in sljit_emit_cmov()
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 800 MOVN = 0x00000000, enumerator
803 MOVN_w = MoveWideImmediateFixed | MOVN,
804 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits,
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| D | assembler-aarch64.h | 2100 MoveWide(rd, imm, shift, MOVN);
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 1927 ### MOVN ### subsection
|