| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86IndirectBranchTracking.cpp | 87 static bool IsCallReturnTwice(llvm::MachineOperand &MOp) { in IsCallReturnTwice() argument
88 if (!MOp.isGlobal()) in IsCallReturnTwice()
90 auto *CalleeFn = dyn_cast<Function>(MOp.getGlobal()); in IsCallReturnTwice()
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| D | X86CmovConversion.cpp | 783 for (auto &MOp : NewMI->uses()) { in convertCmovInstsToBranches() local
784 if (!MOp.isReg()) in convertCmovInstsToBranches()
786 auto It = FalseBBRegRewriteTable.find(MOp.getReg()); in convertCmovInstsToBranches()
790 MOp.setReg(It->second); in convertCmovInstsToBranches()
796 MOp.setIsKill(false); in convertCmovInstsToBranches()
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| D | X86FlagsCopyLowering.cpp | 273 MI.operands(), [&](MachineOperand &MOp) { in splitBlock() argument
274 return MOp.isMBB() && MOp.getMBB() == &UnsplitSucc; in splitBlock()
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| D | X86ISelLowering.cpp | 32198 for (auto &MOp : II.operands()) in EmitSjLjDispatchBlock() local
32199 if (MOp.isReg()) in EmitSjLjDispatchBlock()
32200 DefRegs[MOp.getReg()] = true; in EmitSjLjDispatchBlock()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600OptimizeVectorRegisters.cpp | 278 for (MachineInstr::mop_iterator MOp = RSI.Instr->operands_begin(), in tryMergeUsingCommonSlot() local
279 MOE = RSI.Instr->operands_end(); MOp != MOE; ++MOp) { in tryMergeUsingCommonSlot()
280 if (!MOp->isReg()) in tryMergeUsingCommonSlot()
282 if (PreviousRegSeqByReg[MOp->getReg()].empty()) in tryMergeUsingCommonSlot()
284 for (MachineInstr *MI : PreviousRegSeqByReg[MOp->getReg()]) { in tryMergeUsingCommonSlot()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600OptimizeVectorRegisters.cpp | 294 for (MachineInstr::mop_iterator MOp = RSI.Instr->operands_begin(), in tryMergeUsingCommonSlot() local
295 MOE = RSI.Instr->operands_end(); MOp != MOE; ++MOp) { in tryMergeUsingCommonSlot()
296 if (!MOp->isReg()) in tryMergeUsingCommonSlot()
298 if (PreviousRegSeqByReg[MOp->getReg()].empty()) in tryMergeUsingCommonSlot()
300 for (MachineInstr *MI : PreviousRegSeqByReg[MOp->getReg()]) { in tryMergeUsingCommonSlot()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 203 unsigned MOp; in trySelect() local
206 MOp = Mips::AdduRxRyRz16; in trySelect()
209 MOp = Mips::SubuRxRyRz16; in trySelect()
225 CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, SDValue(AddCarry, 0)); in trySelect()
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| D | MipsSEISelDAGToDAG.h | 42 void selectAddESubE(unsigned MOp, SDValue InFlag, SDValue CmpLHS,
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| D | MipsSEISelDAGToDAG.cpp | 240 void MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag, in selectAddESubE() argument
279 CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, SDValue(AddCarry, 0)); in selectAddESubE()
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 1628 const MachineOperand &MOp = MI->getOperand(i); in runOnMachineFunction() local
1629 if (!MOp.isReg()) in runOnMachineFunction()
1631 unsigned FoldAsLoadDefReg = MOp.getReg(); in runOnMachineFunction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 1759 const MachineOperand &MOp = MI->getOperand(i); in runOnMachineFunction() local
1760 if (!MOp.isReg()) in runOnMachineFunction()
1762 unsigned FoldAsLoadDefReg = MOp.getReg(); in runOnMachineFunction()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 23416 unsigned MOp, FOp; in EmitLoweredAtomicFP() local
23421 MOp = X86::MOVSSmr; in EmitLoweredAtomicFP()
23425 MOp = X86::MOVSDmr; in EmitLoweredAtomicFP()
23446 MIB = BuildMI(*BB, MI, DL, TII->get(MOp)); in EmitLoweredAtomicFP()
24147 for (auto &MOp : II.operands()) in EmitSjLjDispatchBlock() local
24148 if (MOp.isReg()) in EmitSjLjDispatchBlock()
24149 DefRegs[MOp.getReg()] = true; in EmitSjLjDispatchBlock()
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