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Searched refs:MRM2r (Results 1 – 25 of 28) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrControl.td231 def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
238 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
251 def CALL16r_NT : I<0xFF, MRM2r, (outs), (ins GR16 : $dst),
258 def CALL32r_NT : I<0xFF, MRM2r, (outs), (ins GR32 : $dst),
335 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
345 def CALL64r_NT : I<0xFF, MRM2r, (outs), (ins GR64 : $dst),
DX86InstrShiftRotate.td332 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
334 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
336 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
338 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
343 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
345 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt),
347 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
349 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt),
351 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
353 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt),
[all …]
DX86InstrMMX.td409 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
413 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
417 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
DX86InstrFPStack.td334 def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">;
455 def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RSTi:$op),
463 def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RSTi:$op),
602 def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">;
DX86InstrSystem.td397 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
614 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
617 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
DX86InstrArithmetic.td396 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
399 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
402 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
405 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
1186 defm ADC : ArithBinOp_RFF<0x10, 0x12, 0x14, "adc", MRM2r, MRM2m, X86adc_flag,
DX86InstrFormats.td47 def MRM0r : Format<56>; def MRM1r : Format<57>; def MRM2r : Format<58>;
DX86InstrInfo.td2434 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, WriteBLS>;
2435 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem, WriteBLS>, VEX_W;
2665 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", WriteALU, MRM2r, MRM2m>;
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td343 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
345 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt),
348 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
351 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
353 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt),
356 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
359 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
361 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt),
364 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
368 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
[all …]
DX86InstrControl.td204 def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
212 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
283 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
DX86InstrMMX.td471 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
474 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
477 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
DX86InstrFPStack.td292 def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">;
385 def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RST:$op),
393 def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RST:$op),
540 def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RST:$op), "fst\t$op", IIC_FST>;
DX86InstrSystem.td430 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
585 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
588 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
DX86InstrArithmetic.td420 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
423 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
426 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
429 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
1205 defm ADC : ArithBinOp_RFF<0x10, 0x12, 0x14, "adc", MRM2r, MRM2m, X86adc_flag,
DX86InstrSSE.td4050 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4053 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4066 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4101 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4104 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4117 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4154 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4157 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4160 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
DX86InstrInfo.td2222 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2223 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2401 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
DX86InstrFormats.td30 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h295 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator
686 case X86II::MRM2r: case X86II::MRM3r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp870 case X86II::MRM2r: case X86II::MRM3r: in EmitVEXOpcodePrefix()
1021 case X86II::MRM2r: case X86II::MRM3r: in DetermineREXPrefix()
1356 case X86II::MRM2r: case X86II::MRM3r: in encodeInstruction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h666 MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, // Format /0 /1 /2 /3 enumerator
1056 case X86II::MRM2r: case X86II::MRM3r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp1086 case X86II::MRM2r: in emitVEXOpcodePrefix()
1241 case X86II::MRM2r: in determineREXPrefix()
1630 case X86II::MRM2r: in encodeInstruction()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp108 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator
717 case X86Local::MRM2r: in emitInstructionSpecifier()
853 case X86Local::MRM2r: case X86Local::MRM3r: in emitDecodePath()
/external/llvm/test/TableGen/
DTargetInstrInfo.td52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
/external/llvm/docs/TableGen/
DLangIntro.rst547 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
/external/llvm/docs/
DWritingAnLLVMBackend.rst1819 case X86II::MRM2r: case X86II::MRM3r: // a REGISTER r/m operand and

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