| /external/llvm/test/CodeGen/AMDGPU/ |
| D | mubuf.ll | 6 ;;; MUBUF LOAD TESTS
9 ; MUBUF load with an immediate byte offset that fits into 12-bits
20 ; MUBUF load with the largest possible immediate offset
31 ; MUBUF load with an immediate byte offset that doesn't fit into 12-bits
43 ; MUBUF load with a 12-bit immediate offset and a register offset
88 ;;; MUBUF STORE TESTS
91 ; MUBUF store with an immediate byte offset that fits into 12-bits
101 ; MUBUF store with the largest possible immediate offset
112 ; MUBUF store with an immediate byte offset that doesn't fit into 12-bits
123 ; MUBUF store with a 12-bit immediate offset and a register offset
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| D | schedule-global-loads.ll | 24 ; an MUBUF load which does not have a vaddr operand.
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| D | concat_vectors.ll | 5 ; 0x80f000 is the high 32 bits of the resource descriptor used by MUBUF
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_opcodes.py | 43 MUBUF = 10 variable in Format
88 elif self == Format.MUBUF:
1249 MUBUF = { variable
1331 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in MUBUF:
1332 opcode(name, gfx7, gfx9, gfx10, Format.MUBUF, is_atomic = "atomic" in name)
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| D | aco_opt_value_numbering.cpp | 105 case Format::MUBUF: in operator ()()
270 case Format::MUBUF: { in operator ()()
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| D | aco_ir.cpp | 142 case Format::MUBUF: in get_sync_info()
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| D | aco_validate.cpp | 215 … ((instr->format == Format::MUBUF || instr->format == Format::MTBUF) && i == 1); in validate_ir()
429 case Format::MUBUF: { in validate_ir()
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| D | aco_ir.h | 83 MUBUF = 10, enumerator
938 format == Format::MUBUF || in isVMEM()
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| D | aco_print_ir.cpp | 364 case Format::MUBUF: { in print_instr_format_specific()
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| D | aco_insert_NOPs.cpp | 494 bool consider_buf = (instr->format == Format::MUBUF || instr->format == Format::MTBUF) && in handle_instruction_gfx6()
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| D | aco_insert_waitcnt.cpp | 814 case Format::MUBUF: in gen()
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| D | aco_assembler.cpp | 360 case Format::MUBUF: { in emit_instruction()
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| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 55 MUBUF Instructions
57 All non-atomic MUBUF instructions are supported.
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 928 // MUBUF Instructions
2159 (!cast<MUBUF>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset),
2167 (!cast<MUBUF>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset),
2175 (!cast<MUBUF>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset),
2183 (!cast<MUBUF>(opcode # _BOTHEN)
2203 (!cast<MUBUF>(opcode # _OFFSET) $vdata, $rsrc, $soffset, (as_i16imm $offset),
2211 (!cast<MUBUF>(opcode # _IDXEN) $vdata, $vindex, $rsrc, $soffset,
2220 (!cast<MUBUF>(opcode # _OFFEN) $vdata, $voffset, $rsrc, $soffset,
2229 (!cast<MUBUF>(opcode # _BOTHEN)
2252 (!cast<MUBUF>(opcode # _RTN_OFFSET) $vdata_in, $rsrc, $soffset,
[all …]
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| D | SIInstrFormats.td | 38 field bits<1> MUBUF = 0;
74 let TSFlags{16} = MUBUF;
686 class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
691 let MUBUF = 1;
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| D | SIDefines.h | 35 MUBUF = 1 << 16, enumerator
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| D | SIInstrInfo.h | 280 return MI.getDesc().TSFlags & SIInstrFlags::MUBUF; in isMUBUF()
284 return get(Opcode).TSFlags & SIInstrFlags::MUBUF; in isMUBUF()
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| D | CIInstructions.td | 100 // MUBUF Instructions
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| D | SIInstrInfo.td | 2881 // MUBUF classes
2892 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
2899 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
2909 MUBUF <outs, ins, "", pattern>,
2926 MUBUF <outs, ins, asm, []>,
2937 MUBUF <outs, ins, asm, []>,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 38 field bit MUBUF = 0;
150 let TSFlags{16} = MUBUF;
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| D | SIDefines.h | 45 MUBUF = 1 << 16, enumerator
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| D | SIInstrInfo.h | 446 return MI.getDesc().TSFlags & SIInstrFlags::MUBUF; in isMUBUF()
450 return get(Opcode).TSFlags & SIInstrFlags::MUBUF; in isMUBUF()
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| D | BUFInstructions.td | 293 // MUBUF classes
320 let MUBUF = 1;
776 // MUBUF Instructions
1152 // MUBUF Patterns
1851 // MUBUF - GFX10.
1930 // MUBUF - GFX6, GFX7, GFX10.
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| D | AMDGPU.td | 587 // to missing ADDR64 variants of MUBUF instructions.
588 // FIXME: moveToVALU should be able to handle converting addr64 MUBUF
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| /external/mesa3d/docs/relnotes/ |
| D | 20.0.0.rst | 758 - aco: use soffset for MUBUF instructions on SI/CI
2879 - aco: value-number MUBUF instructions
2880 - aco: use MUBUF in some situations instead of splitting vertex fetches
3182 - aco: fix emitting slc for MUBUF instructions on GFX6-GFX7
3188 - aco: add new addr64 bit to MUBUF instructions on GFX6-GFX7
3238 - aco: fix VS input loads with MUBUF on GFX6
3243 - aco: fix MUBUF VS input loads when expanding vec3 to vec4 on GFX6
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