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Searched refs:ORR (Results 1 – 25 of 83) sorted by relevance

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/external/arm-neon-tests/
DInitCache.s19 ORR r0, r0, #(0x1 <<12) ; enable I Cache
21 ORR r0, r0, #(0x1 <<2) ; enable D Cache
23 ORR r0, r0, #0x1 ; enable MMU
31 ORR r0, r0, #2 ; L2EN bit, enable L2 cache
33 ;ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI
34 ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI
35 ORR r0, r0, #(0x1 << 5) ;Enables caching NEON data within the L1 data cache
43 ORR r0, r0, #(0x1 <<11) ; Enable all forms of branch prediction
/external/libxaac/decoder/armv7/
Dixheaacd_complex_ifft_p2.s30 ORR r4, r7, r6, LSL #2
33 ORR r4, r7, r6, LSL #4
37 ORR r4, r7, r6, LSL #8
190 ORR r4, r3, r4, LSL#1
193 ORR r6, r3, r6, LSL#1
196 ORR r5, r3, r5, LSL#1
199 ORR r7, r3, r7, LSL#1
208 ORR r4, r3, r4, LSL#1
211 ORR r8, r3, r8, LSL#1
214 ORR r5, r3, r5, LSL#1
[all …]
Dixheaacd_complex_fft_p2.s30 ORR r4, r7, r6, LSL #2
33 ORR r4, r7, r6, LSL #4
37 ORR r4, r7, r6, LSL #8
190 ORR r4, r3, r4, LSL#1
193 ORR r6, r3, r6, LSL#1
196 ORR r5, r3, r5, LSL#1
199 ORR r7, r3, r7, LSL#1
208 ORR r4, r3, r4, LSL#1
211 ORR r8, r3, r8, LSL#1
214 ORR r5, r3, r5, LSL#1
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Dixheaacd_mps_complex_fft_64_asm.s175 ORR r4, r3, r4, LSL#1
178 ORR r6, r3, r6, LSL#1
181 ORR r5, r3, r5, LSL#1
184 ORR r7, r3, r7, LSL#1
193 ORR r4, r3, r4, LSL#1
196 ORR r8, r3, r8, LSL#1
199 ORR r5, r3, r5, LSL#1
202 ORR r9, r3, r9, LSL#1
211 ORR r4, r3, r4, LSL#1
214 ORR r10, r3, r10, LSL#1
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Dixheaacd_calcmaxspectralline.s54 ORR R4, R4, R1
56 ORR R4, R4, R2
59 ORR R4, R4, R3
66 ORR R4, R4, R2
Dixheaacd_auto_corr.s111 ORR r5, r6, r5
113 ORR r5, r6, r5
115 ORR r5, r9, r5
116 ORR r5, r14, r5
Dixheaacd_expsubbandsamples.s59 ORR r12, r12, r1
86 ORR r12, r12, r3
89 ORR r12, r12, r3
Dixheaacd_enery_calc_per_subband.s85 ORR R6, R6, R4
/external/libxaac/decoder/armv8/
Dixheaacd_calcmaxspectralline.s43 ORR V3.16B, V0.16B, V3.16B
44 ORR V3.16B, V1.16B, V3.16B
53 ORR W4, W4, W1
55 ORR W4, W4, W2
56 ORR W4, W4, W3
65 ORR W4, W4, W2
/external/libhevc/common/arm64/
Dihevc_sao_band_offset_chroma.s176 … ORR v4.8b, v4.8b , v13.8b //band_table.val[3] = vorr_u8(band_table.val[3], au1_cmp)
184 … ORR v3.8b, v3.8b , v14.8b //band_table.val[2] = vorr_u8(band_table.val[2], au1_cmp)
194 … ORR v2.8b, v2.8b , v15.8b //band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
203 … ORR v1.8b, v1.8b , v16.8b //band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
250 … ORR v12.8b, v12.8b , v17.8b //band_table.val[3] = vorr_u8(band_table.val[3], au1_cmp)
258 … ORR v11.8b, v11.8b , v18.8b //band_table.val[2] = vorr_u8(band_table.val[2], au1_cmp)
268 … ORR v10.8b, v10.8b , v19.8b //band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
278 … ORR v9.8b, v9.8b , v20.8b //band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
Dihevc_sao_band_offset_luma.s152 … ORR v4.8b, v4.8b , v25.8b //band_table.val[3] = vorr_u8(band_table.val[3], au1_cmp)
160 … ORR v3.8b, v3.8b , v24.8b //band_table.val[2] = vorr_u8(band_table.val[2], au1_cmp)
170 … ORR v2.8b, v2.8b , v23.8b //band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
180 … ORR v1.8b, v1.8b , v22.8b //band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
/external/llvm/test/CodeGen/AArch64/
Darm64-movi.ll4 ; Tests for MOV-immediate implemented with ORR-immediate.
93 ; Tests for ORR with MOVK.
Dbitfield-insert.ll418 ; Don't generate BFI/BFXIL if the immediate can be encoded in the ORR.
428 ; BFXIL will use the same constant as the ORR, so we don't care how the constant
441 ; as the original ORR are okay.
453 ; to the original ORR are not okay. In this case we would be replacing the
/external/vixl/test/aarch32/config/
Dcond-rd-rn-operand-rm-t32.json85 "Orr", // ORR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
86 // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
236 "Orr", // ORR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
Dcond-rd-rn-operand-const-a32.json42 "Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
Dcond-rd-rn-operand-const-t32.json50 "Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
Dcond-rd-rn-operand-rm-shift-rs-a32.json39 "Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
Dcond-rd-rn-operand-rm-shift-amount-1to32-a32.json41 "Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
Dcond-rd-rn-operand-rm-shift-amount-1to31-a32.json41 "Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
Dcond-rd-rn-operand-rm-shift-amount-1to32-t32.json47 "Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
Dcond-rd-rn-operand-rm-shift-amount-1to31-t32.json47 "Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
/external/pcre/src/sljit/
DsljitNativeARM_64.c115 #define ORR 0xaa000000 macro
783 return push_inst(compiler, ORR | RD(dst) | RN(TMP_ZERO) | RM(arg2)); in emit_op_imm()
807 return push_inst(compiler, (ORR ^ W_OP) | RD(dst) | RN(TMP_ZERO) | RM(arg2)); in emit_op_imm()
854 FAIL_IF(push_inst(compiler, (ORR ^ inv_bits) | RD(dst) | RN(arg1) | RM(arg2))); in emit_op_imm()
1068 FAIL_IF(push_inst(compiler, ORR | RD(SLJIT_S0 - saved_arg_count) | RN(TMP_ZERO) | RM(tmp))); in sljit_emit_enter()
1275 FAIL_IF(push_inst(compiler, ORR | RD(TMP_REG1) | RN(TMP_ZERO) | RM(src))); in sljit_emit_return_to()
1305 FAIL_IF(push_inst(compiler, ORR | RD(TMP_REG1) | RN(TMP_ZERO) | RM(SLJIT_R0))); in sljit_emit_op0()
1310 FAIL_IF(push_inst(compiler, (ORR ^ inv_bits) | RD(TMP_REG1) | RN(TMP_ZERO) | RM(SLJIT_R0))); in sljit_emit_op0()
1553 return push_inst(compiler, (ORR ^ inv_bits) | RD(src_dst) | RN(src_dst) | RM(TMP_REG1)); in sljit_emit_shift_into()
1566 FAIL_IF(push_inst(compiler, ORR | RD(TMP_LR) | RN(TMP_ZERO) | RM(src))); in sljit_emit_op_src()
[all …]
/external/llvm/test/MC/AArch64/
Darm64-aliases.s25 ; ORR Rd, Rn, Rn is a MOV
195 ; ORR is mostly repeating bit sequences and cannot encode -1, so it only
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedPredicates.td362 // ORR Rd, ZR, Rm, LSL #0
430 [// ORR Rd, ZR, #0
/external/OpenCSD/decoder/tests/snapshots/TC2/ds5-dumps/
Dptmv1_0x13.txt233 Instruction 208 S:0xC004F5DE 0xEA480806 0 ORR r8,r8,r6 false
236 Instruction 211 S:0xC004F5E8 0xEA480803 0 ORR r8,r8,r3 false
356 Instruction 329 S:0xC004F5DE 0xEA480806 0 ORR r8,r8,r6 false
359 Instruction 332 S:0xC004F5E8 0xEA480803 0 ORR r8,r8,r3 false
1077 Instruction 1016 S:0xC00089C8 0xF4430370 0 ORR r3,r3,#0xf00000 false
1156 Instruction 1090 S:0xC004F01E 0xEA420200 0 ORR r2,r2,r0 false
1375 Instruction 1303 S:0xC004F5DE 0xEA480806 0 ORR r8,r8,r6 false
1378 Instruction 1306 S:0xC004F5E8 0xEA480803 0 ORR r8,r8,r3 false
1755 Instruction 1679 S:0xC0043EEC 0xEA444510 0 ORR r5,r4,r0,LSR #16 false
1759 Instruction 1683 S:0xC0043EF6 0xEA404103 0 ORR r1,r0,r3,LSL #16 false
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