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Searched refs:Op0 (Results 1 – 25 of 221) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenFastISel.inc121 unsigned fastEmit_AArch64ISD_CALL_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
124 return fastEmitInst_r(AArch64::BLR, &AArch64::GPR64RegClass, Op0, Op0IsKill);
127 unsigned fastEmit_AArch64ISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
129 case MVT::i64: return fastEmit_AArch64ISD_CALL_MVT_i64_r(RetVT, Op0, Op0IsKill);
136 unsigned fastEmit_AArch64ISD_CMEQz_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
140 return fastEmitInst_r(AArch64::CMEQv8i8rz, &AArch64::FPR64RegClass, Op0, Op0IsKill);
145 unsigned fastEmit_AArch64ISD_CMEQz_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
149 return fastEmitInst_r(AArch64::CMEQv16i8rz, &AArch64::FPR128RegClass, Op0, Op0IsKill);
154 unsigned fastEmit_AArch64ISD_CMEQz_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
158 return fastEmitInst_r(AArch64::CMEQv4i16rz, &AArch64::FPR64RegClass, Op0, Op0IsKill);
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenFastISel.inc42 unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
46 return fastEmitInst_r(X86::VPABSBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill);
49 return fastEmitInst_r(X86::PABSBrr, &X86::VR128RegClass, Op0, Op0IsKill);
52 return fastEmitInst_r(X86::VPABSBrr, &X86::VR128RegClass, Op0, Op0IsKill);
57 unsigned fastEmit_ISD_ABS_MVT_v32i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
61 return fastEmitInst_r(X86::VPABSBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill);
64 return fastEmitInst_r(X86::VPABSBYrr, &X86::VR256RegClass, Op0, Op0IsKill);
69 unsigned fastEmit_ISD_ABS_MVT_v64i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
73 return fastEmitInst_r(X86::VPABSBZrr, &X86::VR512RegClass, Op0, Op0IsKill);
78 unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenFastISel.inc80 unsigned fastEmit_ARMISD_CALL_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
84 return fastEmitInst_r(ARM::BLX, &ARM::GPRRegClass, Op0, Op0IsKill);
89 unsigned fastEmit_ARMISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
91 case MVT::i32: return fastEmit_ARMISD_CALL_MVT_i32_r(RetVT, Op0, Op0IsKill);
98 unsigned fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
102 return fastEmitInst_r(ARM::tBX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
105 return fastEmitInst_r(ARM::BMOVPCRX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
108 return fastEmitInst_r(ARM::BX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
113 unsigned fastEmit_ARMISD_CALL_NOLINK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
115 case MVT::i32: return fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(RetVT, Op0, Op0IsKill);
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenFastISel.inc91 unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
95 return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0, Op0IsKill);
100 unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
104 return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0, Op0IsKill);
109 unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
111 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill);
112 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
119 unsigned fastEmit_ISD_BSWAP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
123 return fastEmitInst_r(PPC::XXBRW, &PPC::VSRCRegClass, Op0, Op0IsKill);
128 unsigned fastEmit_ISD_BSWAP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenFastISel.inc55 unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
59 return fastEmitInst_r(Mips::MTC1_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
62 return fastEmitInst_r(Mips::MTC1_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
65 return fastEmitInst_r(Mips::MTC1, &Mips::FGR32RegClass, Op0, Op0IsKill);
70 unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
74 return fastEmitInst_r(Mips::DMTC1, &Mips::FGR64RegClass, Op0, Op0IsKill);
79 unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
83 return fastEmitInst_r(Mips::MFC1_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
86 return fastEmitInst_r(Mips::MFC1_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
89 return fastEmitInst_r(Mips::MFC1, &Mips::GPR32RegClass, Op0, Op0IsKill);
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
DInstructionSimplify.cpp244 if (BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS)) in ExpandBinOp() local
245 if (Op0->getOpcode() == OpcodeToExpand) { in ExpandBinOp()
247 Value *A = Op0->getOperand(0), *B = Op0->getOperand(1), *C = RHS; in ExpandBinOp()
304 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS); in SimplifyAssociativeBinOp() local
308 if (Op0 && Op0->getOpcode() == Opcode) { in SimplifyAssociativeBinOp()
309 Value *A = Op0->getOperand(0); in SimplifyAssociativeBinOp()
310 Value *B = Op0->getOperand(1); in SimplifyAssociativeBinOp()
350 if (Op0 && Op0->getOpcode() == Opcode) { in SimplifyAssociativeBinOp()
351 Value *A = Op0->getOperand(0); in SimplifyAssociativeBinOp()
352 Value *B = Op0->getOperand(1); in SimplifyAssociativeBinOp()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/
DInstCombineMulDivRem.cpp186 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitMul() local
188 BinaryOperator *BO = BinaryOperator::CreateNeg(Op0, I.getName()); in visitMul()
241 if (Op0->hasOneUse()) { in visitMul()
244 if (match(Op0, m_Sub(m_Value(Y), m_Value(X)))) in visitMul()
246 else if (match(Op0, m_Add(m_Value(Y), m_ConstantInt(C1)))) in visitMul()
268 if (match(Op0, m_OneUse(m_Add(m_Value(X), m_Constant(C1))))) { in visitMul()
280 if (match(Op0, m_Neg(m_Value(X))) && match(Op1, m_Constant(Op1C))) in visitMul()
284 if (match(Op0, m_Neg(m_Value(X))) && match(Op1, m_Neg(m_Value(Y)))) { in visitMul()
287 cast<OverflowingBinaryOperator>(Op0)->hasNoSignedWrap() && in visitMul()
302 BinaryOperator *Div = dyn_cast<BinaryOperator>(Op0); in visitMul()
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DInstCombineAddSub.cpp828 Value *Op0 = Add.getOperand(0), *Op1 = Add.getOperand(1); in foldNoWrapAdd() local
839 match(Op0, m_OneUse(m_ZExt(m_NUWAdd(m_Value(X), m_APInt(C2))))) && in foldNoWrapAdd()
849 if (match(Op0, m_OneUse(m_SExt(m_NSWAdd(m_Value(X), m_Constant(NarrowC)))))) { in foldNoWrapAdd()
856 if (match(Op0, m_OneUse(m_ZExt(m_NUWAdd(m_Value(X), m_Constant(NarrowC)))))) { in foldNoWrapAdd()
867 Value *Op0 = Add.getOperand(0), *Op1 = Add.getOperand(1); in foldAddWithConstant() local
879 if (match(Op0, m_Sub(m_Constant(Op00C), m_Value(X)))) in foldAddWithConstant()
885 if (match(Op0, m_OneUse(m_Sub(m_Value(X), m_Value(Y)))) && in foldAddWithConstant()
890 if (match(Op0, m_ZExt(m_Value(X))) && in foldAddWithConstant()
894 if (match(Op0, m_SExt(m_Value(X))) && in foldAddWithConstant()
899 if (match(Op0, m_Not(m_Value(X)))) in foldAddWithConstant()
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DInstCombineShifts.cpp364 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonShiftTransforms() local
365 assert(Op0->getType() == Op1->getType()); in commonShiftTransforms()
371 return BinaryOperator::Create(I.getOpcode(), Op0, NewExt); in commonShiftTransforms()
379 if (isa<Constant>(Op0)) in commonShiftTransforms()
385 if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I)) in commonShiftTransforms()
396 if (match(Op0, m_Constant()) && match(Op1, m_Add(m_Value(A), m_Constant(C)))) in commonShiftTransforms()
400 I.getOpcode(), Builder.CreateBinOp(I.getOpcode(), Op0, C), A); in commonShiftTransforms()
682 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1, in FoldShiftByConstant() argument
693 canEvaluateShifted(Op0, Op1C->getZExtValue(), isLeftShift, *this, &I)) { in FoldShiftByConstant()
697 << *Op0 << "\n SH: " << I << "\n"); in FoldShiftByConstant()
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DInstCombineAndOrXor.cpp1163 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); in foldAndOfICmps() local
1166 return getNewICmpValue(Code, IsSigned, Op0, Op1, Builder); in foldAndOfICmps()
1421 Value *Op0 = BO.getOperand(0), *Op1 = BO.getOperand(1), *X; in reassociateFCmps() local
1424 std::swap(Op0, Op1); in reassociateFCmps()
1430 if (!match(Op0, m_FCmp(Pred, m_Value(X), m_AnyZeroFP())) || Pred != NanPred || in reassociateFCmps()
1449 NewFCmpInst->copyIRFlags(Op0); in reassociateFCmps()
1539 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in foldCastedBitwiseLogic() local
1540 CastInst *Cast0 = dyn_cast<CastInst>(Op0); in foldCastedBitwiseLogic()
1604 Value *Op0 = I.getOperand(0); in foldAndToXor() local
1619 if (Op0->hasOneUse() || Op1->hasOneUse()) in foldAndToXor()
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/external/llvm/lib/Analysis/
DInstructionSimplify.cpp149 if (BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS)) in ExpandBinOp() local
150 if (Op0->getOpcode() == OpcodeToExpand) { in ExpandBinOp()
152 Value *A = Op0->getOperand(0), *B = Op0->getOperand(1), *C = RHS; in ExpandBinOp()
208 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS); in SimplifyAssociativeBinOp() local
212 if (Op0 && Op0->getOpcode() == Opcode) { in SimplifyAssociativeBinOp()
213 Value *A = Op0->getOperand(0); in SimplifyAssociativeBinOp()
214 Value *B = Op0->getOperand(1); in SimplifyAssociativeBinOp()
254 if (Op0 && Op0->getOpcode() == Opcode) { in SimplifyAssociativeBinOp()
255 Value *A = Op0->getOperand(0); in SimplifyAssociativeBinOp()
256 Value *B = Op0->getOperand(1); in SimplifyAssociativeBinOp()
[all …]
/external/llvm/lib/Transforms/InstCombine/
DInstCombineMulDivRem.cpp177 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitMul() local
182 if (Value *V = SimplifyMulInst(Op0, Op1, DL, TLI, DT, AC)) in visitMul()
190 BinaryOperator *BO = BinaryOperator::CreateNeg(Op0, I.getName()); in visitMul()
252 if (Op0->hasOneUse()) { in visitMul()
255 if (match(Op0, m_Sub(m_Value(Y), m_Value(X)))) in visitMul()
257 else if (match(Op0, m_Add(m_Value(Y), m_ConstantInt(C1)))) in visitMul()
271 if (SelectInst *SI = dyn_cast<SelectInst>(Op0)) in visitMul()
275 if (isa<PHINode>(Op0)) in visitMul()
283 if (match(Op0, m_OneUse(m_Add(m_Value(X), m_Constant(C1))))) { in visitMul()
293 if (Value *Op0v = dyn_castNegVal(Op0)) { // -X * -Y = X*Y in visitMul()
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DInstCombineAndOrXor.cpp878 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); in FoldAndOfICmps() local
881 return getNewICmpValue(isSigned, Code, Op0, Op1, Builder); in FoldAndOfICmps()
1162 Value *Op0 = I.getOperand(0); in matchDeMorgansLaws() local
1165 if (Value *Op0NotVal = dyn_castNotVal(Op0)) in matchDeMorgansLaws()
1167 if (Op0->hasOneUse() && Op1->hasOneUse()) { in matchDeMorgansLaws()
1179 if (match(Op0, m_OneUse(m_Xor(m_ZExt(m_Value(A)), m_ConstantInt(C1)))) && in matchDeMorgansLaws()
1202 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in foldCastedBitwiseLogic() local
1203 CastInst *Cast0 = dyn_cast<CastInst>(Op0); in foldCastedBitwiseLogic()
1221 if ((match(Op0, m_BitCast(m_Value(BC))) && match(Op1, m_Constant(C)))) { in foldCastedBitwiseLogic()
1283 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in foldBoolSextMaskToSelect() local
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DInstCombineShifts.cpp26 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonShiftTransforms() local
33 if (isa<Constant>(Op0)) in commonShiftTransforms()
39 if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I)) in commonShiftTransforms()
322 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1, in FoldShiftByConstant() argument
340 CanEvaluateShifted(Op0, COp1->getZExtValue(), isLeftShift, *this, &I)) { in FoldShiftByConstant()
342 " to eliminate shift:\n IN: " << *Op0 << "\n SH: " << I <<"\n"); in FoldShiftByConstant()
345 I, GetShiftedValue(Op0, COp1->getZExtValue(), isLeftShift, *this, DL)); in FoldShiftByConstant()
350 uint32_t TypeBits = Op0->getType()->getScalarSizeInBits(); in FoldShiftByConstant()
356 if (BinaryOperator *BO = dyn_cast<BinaryOperator>(Op0)) in FoldShiftByConstant()
363 if (SelectInst *SI = dyn_cast<SelectInst>(Op0)) in FoldShiftByConstant()
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DInstCombineCompares.cpp2950 static bool swapMayExposeCSEOpportunities(const Value * Op0, in swapMayExposeCSEOpportunities() argument
2954 if (Op0->getType()->isPointerTy()) in swapMayExposeCSEOpportunities()
2964 for (const User *U : Op0->users()) { in swapMayExposeCSEOpportunities()
2972 if (BinOp->getOperand(Op1Idx) == Op0) { in swapMayExposeCSEOpportunities()
3105 Value *Op0 = I.getOperand(0); in canonicalizeCmpWithConstant() local
3150 return new ICmpInst(NewPred, Op0, ConstantExpr::getAdd(Op1C, OneOrNegOne)); in canonicalizeCmpWithConstant()
3155 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitICmpInst() local
3156 unsigned Op0Cplxity = getComplexity(Op0); in visitICmpInst()
3163 (Op0Cplxity == Op1Cplxity && swapMayExposeCSEOpportunities(Op0, Op1))) { in visitICmpInst()
3165 std::swap(Op0, Op1); in visitICmpInst()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZTDC.cpp123 Value *Op0 = I.getOperand(0); in convertFCmp() local
130 auto &Sem = Op0->getType()->getFltSemantics(); in convertFCmp()
216 if (CallInst *CI = dyn_cast<CallInst>(Op0)) { in convertFCmp()
222 Op0 = CI->getArgOperand(0); in convertFCmp()
229 converted(&I, Op0, Mask, Worthy); in convertFCmp()
233 Value *Op0 = I.getOperand(0); in convertICmp() local
239 if (auto *Cast = dyn_cast<BitCastInst>(Op0)) { in convertICmp()
259 } else if (auto *CI = dyn_cast<CallInst>(Op0)) { in convertICmp()
288 Value *Op0, *Op1; in convertLogicOp() local
291 std::tie(Op0, Mask0, Worthy0) = ConvertedInsts[cast<Instruction>(I.getOperand(0))]; in convertLogicOp()
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZTDC.cpp123 Value *Op0 = I.getOperand(0); in convertFCmp() local
130 auto &Sem = Op0->getType()->getFltSemantics(); in convertFCmp()
216 if (CallInst *CI = dyn_cast<CallInst>(Op0)) { in convertFCmp()
222 Op0 = CI->getArgOperand(0); in convertFCmp()
229 converted(&I, Op0, Mask, Worthy); in convertFCmp()
233 Value *Op0 = I.getOperand(0); in convertICmp() local
239 if (auto *Cast = dyn_cast<BitCastInst>(Op0)) { in convertICmp()
259 } else if (auto *CI = dyn_cast<CallInst>(Op0)) { in convertICmp()
288 Value *Op0, *Op1; in convertLogicOp() local
291 std::tie(Op0, Mask0, Worthy0) = ConvertedInsts[cast<Instruction>(I.getOperand(0))]; in convertLogicOp()
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/external/llvm/lib/Transforms/Scalar/
DScalarizer.cpp73 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, in operator ()()
75 return Builder.CreateFCmp(FCI.getPredicate(), Op0, Op1, Name); in operator ()()
84 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, in operator ()()
86 return Builder.CreateICmp(ICI.getPredicate(), Op0, Op1, Name); in operator ()()
95 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, in operator ()()
97 return Builder.CreateBinOp(BO.getOpcode(), Op0, Op1, Name); in operator ()()
384 Scatterer Op0 = scatter(&I, I.getOperand(0)); in splitBinary() local
386 assert(Op0.size() == NumElems && "Mismatched binary operation"); in splitBinary()
391 Res[Elem] = Split(Builder, Op0[Elem], Op1[Elem], in splitBinary()
412 Scatterer Op0 = scatter(&SI, SI.getOperand(0)); in visitSelectInst() local
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/
DScalarizer.cpp108 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, in operator ()()
110 return Builder.CreateFCmp(FCI.getPredicate(), Op0, Op1, Name); in operator ()()
121 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, in operator ()()
123 return Builder.CreateICmp(ICI.getPredicate(), Op0, Op1, Name); in operator ()()
146 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, in operator ()()
148 return Builder.CreateBinOp(BO.getOpcode(), Op0, Op1, Name); in operator ()()
488 Scatterer Op0 = scatter(&I, I.getOperand(0)); in splitBinary() local
490 assert(Op0.size() == NumElems && "Mismatched binary operation"); in splitBinary()
495 Res[Elem] = Split(Builder, Op0[Elem], Op1[Elem], in splitBinary()
587 Scatterer Op0 = scatter(&SI, SI.getOperand(0)); in visitSelectInst() local
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/external/llvm/include/llvm/CodeGen/
DFastISel.h345 virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
350 virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
356 virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
362 virtual unsigned fastEmit_rf(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
369 unsigned Op0, bool Op0IsKill, unsigned Op1,
377 unsigned fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill,
398 const TargetRegisterClass *RC, unsigned Op0,
404 const TargetRegisterClass *RC, unsigned Op0,
410 const TargetRegisterClass *RC, unsigned Op0,
417 const TargetRegisterClass *RC, unsigned Op0,
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/external/llvm/lib/CodeGen/GlobalISel/
DMachineIRBuilder.cpp73 unsigned Op0, unsigned Op1) { in buildInstr() argument
74 return buildInstr(Opcode, nullptr, Res, Op0, Op1); in buildInstr()
78 unsigned Res, unsigned Op0, in buildInstr() argument
83 .addReg(Op0) in buildInstr()
89 unsigned Op0) { in buildInstr() argument
91 MachineInstrBuilder(getMF(), NewMI).addReg(Res, RegState::Define).addReg(Op0); in buildInstr()
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.cpp93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
95 Ops[1].getAsInteger(10, Op0); in parseGenericRegister()
100 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
107 uint32_t Op0 = (Bits >> 14) & 0x3; in genericRegisterString() local
113 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" + in genericRegisterString()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.cpp135 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
137 Ops[1].getAsInteger(10, Op0); in parseGenericRegister()
142 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
149 uint32_t Op0 = (Bits >> 14) & 0x3; in genericRegisterString() local
155 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" + in genericRegisterString()
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp425 unsigned Op0 = getRegForValue(I->getOperand(0)); in selectBinaryOp() local
426 if (!Op0) // Unhandled operand. Halt "fast" selection and bail. in selectBinaryOp()
448 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, in selectBinaryOp()
461 ISDOpcode, Op0, Op0IsKill, CF); in selectBinaryOp()
476 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill); in selectBinaryOp()
1298 unsigned Op0 = getRegForValue(I->getOperand(0)); in selectBitCast() local
1299 if (!Op0) // Unhandled operand. Halt "fast" selection and bail. in selectBitCast()
1312 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0); in selectBitCast()
1318 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); in selectBitCast()
1534 const Value *Op0 = EVI->getOperand(0); in selectExtractValue() local
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/external/llvm/lib/IR/
DAutoUpgrade.cpp512 Value *Op0, Value *Op1) { in EmitX86Select() argument
516 return Op0; in EmitX86Select()
518 Mask = getX86MaskVec(Builder, Mask, Op0->getType()->getVectorNumElements()); in EmitX86Select()
519 return Builder.CreateSelect(Mask, Op0, Op1); in EmitX86Select()
523 Value *Op0, Value *Op1, Value *Shift, in UpgradeX86PALIGNRIntrinsics() argument
527 unsigned NumElts = Op0->getType()->getVectorNumElements(); in UpgradeX86PALIGNRIntrinsics()
533 return llvm::Constant::getNullValue(Op0->getType()); in UpgradeX86PALIGNRIntrinsics()
539 Op1 = Op0; in UpgradeX86PALIGNRIntrinsics()
540 Op0 = llvm::Constant::getNullValue(Op0->getType()); in UpgradeX86PALIGNRIntrinsics()
554 Value *Align = Builder.CreateShuffleVector(Op1, Op0, in UpgradeX86PALIGNRIntrinsics()
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