| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 47 unsigned Opc = MI.getOpcode(); in isLoadFromStackSlot() local
49 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
69 unsigned Opc = MI.getOpcode(); in isStoreToStackSlot() local
71 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
93 Opc = Mips::MOVE16_MM; in copyPhysReg()
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
97 Opc = Mips::CFC1; in copyPhysReg()
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| D | Mips16InstrInfo.cpp | 73 unsigned Opc = 0; in copyPhysReg() local
77 Opc = Mips::MoveR3216; in copyPhysReg()
80 Opc = Mips::Move32R16; in copyPhysReg()
83 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
86 Opc = Mips::Mflo16, SrcReg = 0; in copyPhysReg()
88 assert(Opc && "Cannot copy registers"); in copyPhysReg()
90 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg()
115 unsigned Opc = 0; in storeRegToStack() local
117 Opc = Mips::SwRxSpImmX16; in storeRegToStack()
118 assert(Opc && "Register class not handled!"); in storeRegToStack()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 43 unsigned Opc = MI.getOpcode(); in isLoadFromStackSlot() local
45 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
65 unsigned Opc = MI.getOpcode(); in isStoreToStackSlot() local
67 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
83 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
89 Opc = Mips::MOVE16_MM; in copyPhysReg()
91 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
93 Opc = Mips::CFC1; in copyPhysReg()
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| D | Mips16InstrInfo.cpp | 63 unsigned Opc = 0; in copyPhysReg() local
67 Opc = Mips::MoveR3216; in copyPhysReg()
70 Opc = Mips::Move32R16; in copyPhysReg()
73 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
77 Opc = Mips::Mflo16, SrcReg = 0; in copyPhysReg()
80 assert(Opc && "Cannot copy registers"); in copyPhysReg()
82 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg()
100 unsigned Opc = 0; in storeRegToStack() local
102 Opc = Mips::SwRxSpImmX16; in storeRegToStack()
103 assert(Opc && "Register class not handled!"); in storeRegToStack()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelDAGToDAG.cpp | 748 unsigned Opc; in SelectAddrSpaceCast() local
752 Opc = TM.is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes; in SelectAddrSpaceCast()
755 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_shared_yes_6432 in SelectAddrSpaceCast()
760 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_const_yes_6432 in SelectAddrSpaceCast()
765 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_local_yes_6432 in SelectAddrSpaceCast()
770 ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), in SelectAddrSpaceCast()
777 unsigned Opc; in SelectAddrSpaceCast() local
781 Opc = TM.is64Bit() ? NVPTX::cvta_to_global_yes_64 in SelectAddrSpaceCast()
785 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_to_shared_yes_3264 in SelectAddrSpaceCast()
790 Opc = TM.is64Bit() ? (useShortPointers() ? NVPTX::cvta_to_const_yes_3264 in SelectAddrSpaceCast()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 114 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
487 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode() argument
488 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
512 static inline bool isVPTOpcode(int Opc) { in isVPTOpcode() argument
513 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 || in isVPTOpcode()
514 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 || in isVPTOpcode()
515 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 || in isVPTOpcode()
516 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 || in isVPTOpcode()
517 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 || in isVPTOpcode()
518 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r || in isVPTOpcode()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelDAGToDAG.cpp | 622 unsigned Opc; in SelectAddrSpaceCast() local
626 Opc = TM.is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes; in SelectAddrSpaceCast()
629 Opc = TM.is64Bit() ? NVPTX::cvta_shared_yes_64 : NVPTX::cvta_shared_yes; in SelectAddrSpaceCast()
632 Opc = TM.is64Bit() ? NVPTX::cvta_const_yes_64 : NVPTX::cvta_const_yes; in SelectAddrSpaceCast()
635 Opc = TM.is64Bit() ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes; in SelectAddrSpaceCast()
638 ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), in SelectAddrSpaceCast()
645 unsigned Opc; in SelectAddrSpaceCast() local
649 Opc = TM.is64Bit() ? NVPTX::cvta_to_global_yes_64 in SelectAddrSpaceCast()
653 Opc = TM.is64Bit() ? NVPTX::cvta_to_shared_yes_64 in SelectAddrSpaceCast()
657 Opc = in SelectAddrSpaceCast()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 105 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
420 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode() argument
421 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
425 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode() argument
426 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; in isCondBranchOpcode()
430 bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode() argument
431 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd || in isJumpTableBranchOpcode()
432 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT; in isJumpTableBranchOpcode()
436 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode() argument
437 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; in isIndirectBranchOpcode()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 386 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64 in materializeLoadStoreOperands() local
388 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg) in materializeLoadStoreOperands()
605 unsigned Opc = in fastMaterializeAlloca() local
607 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeAlloca()
624 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64 in fastMaterializeConstant() local
626 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeConstant()
659 unsigned Opc; in fastLowerArguments() local
666 Opc = WebAssembly::ARGUMENT_i32; in fastLowerArguments()
670 Opc = WebAssembly::ARGUMENT_i64; in fastLowerArguments()
674 Opc = WebAssembly::ARGUMENT_f32; in fastLowerArguments()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 331 unsigned Opc = Subtarget->hasAddr64() ? in materializeLoadStoreOperands() local
334 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg) in materializeLoadStoreOperands()
531 unsigned Opc = Subtarget->hasAddr64() ? in fastMaterializeAlloca() local
534 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeAlloca()
547 unsigned Opc = Subtarget->hasAddr64() ? in fastMaterializeConstant() local
550 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeConstant()
581 unsigned Opc; in fastLowerArguments() local
588 Opc = WebAssembly::ARGUMENT_I32; in fastLowerArguments()
592 Opc = WebAssembly::ARGUMENT_I64; in fastLowerArguments()
596 Opc = WebAssembly::ARGUMENT_F32; in fastLowerArguments()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CSEMIRBuilder.cpp | 51 bool CSEMIRBuilder::canPerformCSEForOpc(unsigned Opc) const { in canPerformCSEForOpc()
53 if (!CSEInfo || !CSEInfo->shouldCSE(Opc)) in canPerformCSEForOpc()
83 unsigned Opc) const { in profileMBBOpcode()
87 B.addNodeIDOpcode(Opc); in profileMBBOpcode()
90 void CSEMIRBuilder::profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps, in profileEverything() argument
95 profileMBBOpcode(B, Opc); in profileEverything()
137 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc, in buildInstr() argument
141 switch (Opc) { in buildInstr()
160 if (Optional<APInt> Cst = ConstantFoldBinOp(Opc, SrcOps[0].getReg(), in buildInstr()
172 ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI())) in buildInstr()
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| D | CSEInfo.cpp | 36 bool CSEConfigFull::shouldCSEOpc(unsigned Opc) { in shouldCSEOpc() argument
37 switch (Opc) { in shouldCSEOpc()
66 bool CSEConfigConstantOnly::shouldCSEOpc(unsigned Opc) { in shouldCSEOpc() argument
67 return Opc == TargetOpcode::G_CONSTANT; in shouldCSEOpc()
164 void GISelCSEInfo::countOpcodeHit(unsigned Opc) { in countOpcodeHit() argument
166 if (OpcodeHitTable.count(Opc)) in countOpcodeHit()
167 OpcodeHitTable[Opc] += 1; in countOpcodeHit()
169 OpcodeHitTable[Opc] = 1; in countOpcodeHit()
218 bool GISelCSEInfo::shouldCSE(unsigned Opc) const { in shouldCSE()
220 if (!isPreISelGenericOpcode(Opc)) in shouldCSE()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 158 static unsigned getBranchDisplacementBits(unsigned Opc) { in getBranchDisplacementBits() argument
159 switch (Opc) { in getBranchDisplacementBits()
439 unsigned Opc = 0; in canFoldIntoCSel() local
456 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr; in canFoldIntoCSel()
466 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr; in canFoldIntoCSel()
484 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr; in canFoldIntoCSel()
490 assert(Opc && SrcOpNum && "Missing parameters"); in canFoldIntoCSel()
494 return Opc; in canFoldIntoCSel()
623 unsigned Opc = 0; in insertSelect() local
628 Opc = AArch64::CSELXr; in insertSelect()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 113 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
457 unsigned Opc; in PPCEmitLoad() local
482 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8; in PPCEmitLoad()
485 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8) in PPCEmitLoad()
489 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8) in PPCEmitLoad()
491 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0)) in PPCEmitLoad()
495 Opc = PPC::LD; in PPCEmitLoad()
501 Opc = PPCSubTarget->hasSPE() ? PPC::SPELWZ : PPC::LFS; in PPCEmitLoad()
504 Opc = FP64LoadOpc; in PPCEmitLoad()
517 bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS; in PPCEmitLoad()
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| D | PPCCTRLoops.cpp | 148 unsigned Opc = I->getOpcode(); in verifyCTRBranch() local
149 if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop) { in verifyCTRBranch()
210 unsigned Opc = MII->getOpcode(); in runOnMachineFunction() local
211 if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ || in runOnMachineFunction()
212 Opc == PPC::BDZ8 || Opc == PPC::BDZ) in runOnMachineFunction()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 310 unsigned Opc = 0; in canFoldIntoCSel() local
326 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr; in canFoldIntoCSel()
336 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr; in canFoldIntoCSel()
353 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr; in canFoldIntoCSel()
359 assert(Opc && SrcOpNum && "Missing parameters"); in canFoldIntoCSel()
363 return Opc; in canFoldIntoCSel()
491 unsigned Opc = 0; in insertSelect() local
496 Opc = AArch64::CSELXr; in insertSelect()
500 Opc = AArch64::CSELWr; in insertSelect()
504 Opc = AArch64::FCSELDrrr; in insertSelect()
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| D | AArch64ConditionalCompares.cpp | 577 unsigned Opc = 0; in convert() local
581 Opc = AArch64::SUBSWri; in convert()
585 Opc = AArch64::SUBSXri; in convert()
590 const MCInstrDesc &MCID = TII->get(Opc); in convert()
609 unsigned Opc = 0; in convert() local
615 case AArch64::SUBSWri: Opc = AArch64::CCMPWi; break; in convert()
616 case AArch64::SUBSWrr: Opc = AArch64::CCMPWr; break; in convert()
617 case AArch64::SUBSXri: Opc = AArch64::CCMPXi; break; in convert()
618 case AArch64::SUBSXrr: Opc = AArch64::CCMPXr; break; in convert()
619 case AArch64::ADDSWri: Opc = AArch64::CCMNWi; break; in convert()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 114 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
465 unsigned Opc; in PPCEmitLoad() local
489 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8; in PPCEmitLoad()
492 Opc = (IsZExt ? in PPCEmitLoad()
497 Opc = (IsZExt ? in PPCEmitLoad()
500 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0)) in PPCEmitLoad()
504 Opc = PPC::LD; in PPCEmitLoad()
510 Opc = PPC::LFS; in PPCEmitLoad()
513 Opc = FP64LoadOpc; in PPCEmitLoad()
526 bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS; in PPCEmitLoad()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 97 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
129 bool X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned Opc,
357 unsigned Opc = 0; in X86FastEmitLoad() local
363 Opc = X86::MOV8rm; in X86FastEmitLoad()
367 Opc = X86::MOV16rm; in X86FastEmitLoad()
371 Opc = X86::MOV32rm; in X86FastEmitLoad()
376 Opc = X86::MOV64rm; in X86FastEmitLoad()
381 Opc = HasAVX ? X86::VMOVSSrm : X86::MOVSSrm; in X86FastEmitLoad()
384 Opc = X86::LD_Fp32m; in X86FastEmitLoad()
390 Opc = HasAVX ? X86::VMOVSDrm : X86::MOVSDrm; in X86FastEmitLoad()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCFrameLowering.cpp | 138 unsigned Opc = ARC::SUB_rrlimm; in emitPrologue() local
140 Opc = ARC::SUB_rru6; in emitPrologue()
142 Opc = ARC::SUB_rrs12; in emitPrologue()
143 BuildMI(MBB, MBBI, dl, TII->get(Opc), ARC::SP) in emitPrologue()
255 unsigned Opc = ARC::SUB_rrlimm; in emitEpilogue() local
257 Opc = ARC::SUB_rru6; in emitEpilogue()
258 BuildMI(MBB, MBBI, DebugLoc(), TII->get(Opc), ARC::SP) in emitEpilogue()
283 unsigned Opc = ARC::ADD_rrlimm; in emitEpilogue() local
285 Opc = ARC::ADD_rru6; in emitEpilogue()
287 Opc = ARC::ADD_rrs12; in emitEpilogue()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 97 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
131 bool X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned Opc,
333 unsigned Opc = 0; in X86FastEmitLoad() local
337 Opc = X86::MOV8rm; in X86FastEmitLoad()
340 Opc = X86::MOV16rm; in X86FastEmitLoad()
343 Opc = X86::MOV32rm; in X86FastEmitLoad()
347 Opc = X86::MOV64rm; in X86FastEmitLoad()
351 Opc = HasAVX512 ? X86::VMOVSSZrm_alt : in X86FastEmitLoad()
355 Opc = X86::LD_Fp32m; in X86FastEmitLoad()
359 Opc = HasAVX512 ? X86::VMOVSDZrm_alt : in X86FastEmitLoad()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | XRayInstrumentation.cpp | 96 unsigned Opc = 0; in replaceRetWithPatchableRet() local
101 Opc = TargetOpcode::PATCHABLE_RET; in replaceRetWithPatchableRet()
106 Opc = TargetOpcode::PATCHABLE_TAIL_CALL; in replaceRetWithPatchableRet()
108 if (Opc != 0) { in replaceRetWithPatchableRet()
109 auto MIB = BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)) in replaceRetWithPatchableRet()
129 unsigned Opc = 0; in prependRetWithPatchableExit() local
132 Opc = TargetOpcode::PATCHABLE_FUNCTION_EXIT; in prependRetWithPatchableExit()
135 Opc = TargetOpcode::PATCHABLE_TAIL_CALL; in prependRetWithPatchableExit()
137 if (Opc != 0) { in prependRetWithPatchableExit()
140 BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)); in prependRetWithPatchableExit()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCFGOptimizer.cpp | 61 static bool IsConditionalBranch(int Opc) { in IsConditionalBranch() argument
62 return (Opc == Hexagon::J2_jumpt) || (Opc == Hexagon::J2_jumpf) in IsConditionalBranch()
63 || (Opc == Hexagon::J2_jumptnewpt) || (Opc == Hexagon::J2_jumpfnewpt); in IsConditionalBranch()
67 static bool IsUnconditionalJump(int Opc) { in IsUnconditionalJump() argument
68 return (Opc == Hexagon::J2_jump); in IsUnconditionalJump()
115 int Opc = MI.getOpcode(); in runOnMachineFunction() local
116 if (IsConditionalBranch(Opc)) { in runOnMachineFunction()
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| D | HexagonSplitConst32AndConst64.cpp | 90 int Opc = MI.getOpcode(); in runOnMachineFunction() local
91 if (Opc == Hexagon::CONST32_Int_Real && in runOnMachineFunction()
106 else if (Opc == Hexagon::CONST32_Int_Real || in runOnMachineFunction()
107 Opc == Hexagon::CONST32_Float_Real) { in runOnMachineFunction()
113 if (Opc == Hexagon::CONST32_Float_Real) { in runOnMachineFunction()
126 else if (Opc == Hexagon::CONST64_Int_Real || in runOnMachineFunction()
127 Opc == Hexagon::CONST64_Float_Real) { in runOnMachineFunction()
133 if (Opc == Hexagon::CONST64_Float_Real) { in runOnMachineFunction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| D | WebAssemblyMCTargetDesc.h | 150 inline unsigned GetDefaultP2AlignAny(unsigned Opc) { in GetDefaultP2AlignAny() argument
151 switch (Opc) { in GetDefaultP2AlignAny()
364 inline unsigned GetDefaultP2Align(unsigned Opc) { in GetDefaultP2Align() argument
365 auto Align = GetDefaultP2AlignAny(Opc); in GetDefaultP2Align()
372 inline bool isArgument(unsigned Opc) { in isArgument() argument
373 switch (Opc) { in isArgument()
402 inline bool isCopy(unsigned Opc) { in isCopy() argument
403 switch (Opc) { in isCopy()
422 inline bool isTee(unsigned Opc) { in isTee() argument
423 switch (Opc) { in isTee()
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