Searched refs:PIPE_CONTROL_STATE_CACHE_INVALIDATE (Results 1 – 10 of 10) sorted by relevance
63 PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22), enumerator73 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | \
222 if (IS_GEN_BETWEEN(7, 8) && (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE)) { in genX()483 flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE; in genX()
540 PIPE_CONTROL_STATE_CACHE_INVALIDATE | in brw_emit_select_pipeline()897 PIPE_CONTROL_STATE_CACHE_INVALIDATE | in brw_upload_state_base_address()
109 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in setup_l3_config()
3274 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE); in intel_miptree_set_clear_color()
2230 PIPE_CONTROL_STATE_CACHE_INVALIDATE);
299 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in iris_flush_all_caches()
317 PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22), enumerator330 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | \
470 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in flush_after_state_base_change()665 PIPE_CONTROL_STATE_CACHE_INVALIDATE | in emit_pipeline_select()4673 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in surf_state_update_clear_value()7303 if (GEN_GEN <= 8 && (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE)) { in iris_emit_raw_pipe_control()7533 (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE) ? "State " : "", in iris_emit_raw_pipe_control()7573 flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE; in iris_emit_raw_pipe_control()
79 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1 << 2) macro