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Searched refs:PIPE_CONTROL_VF_CACHE_INVALIDATE (Results 1 – 12 of 12) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.h61 PIPE_CONTROL_VF_CACHE_INVALIDATE = (1 << 20), enumerator
74 PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
DgenX_pipe_control.c107 if (GEN_GEN == 9 && (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) { in genX()
139 if (IS_GEN_BETWEEN(8, 10) && (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) { in genX()
484 pc.VFCacheInvalidationEnable = flags & PIPE_CONTROL_VF_CACHE_INVALIDATE; in genX()
Dbrw_pipe_control.c367 PIPE_CONTROL_VF_CACHE_INVALIDATE | in brw_emit_mi_flush()
DgenX_blorp_exec.c229 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_CS_STALL); in blorp_vf_invalidate_for_vb_48b_transitions()
Dbrw_program.c357 bits |= PIPE_CONTROL_VF_CACHE_INVALIDATE; in brw_memory_barrier()
DgenX_state_upload.c438 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_CS_STALL); in vf_invalidate_for_vb_48bit_transitions()
450 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_VF_CACHE_INVALIDATE); in vf_invalidate_for_ib_48bit_transition()
/external/mesa3d/src/gallium/drivers/iris/
Diris_pipe_control.c295 PIPE_CONTROL_VF_CACHE_INVALIDATE | in iris_flush_all_caches()
341 bits |= PIPE_CONTROL_VF_CACHE_INVALIDATE; in iris_memory_barrier()
Diris_context.h315 PIPE_CONTROL_VF_CACHE_INVALIDATE = (1 << 20), enumerator
332 PIPE_CONTROL_VF_CACHE_INVALIDATE | \
Diris_blorp.c221 PIPE_CONTROL_VF_CACHE_INVALIDATE | in blorp_vf_invalidate_for_vb_48b_transitions()
Diris_state.c6272 flush_flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE | in iris_upload_dirty_render_state()
6510 PIPE_CONTROL_VF_CACHE_INVALIDATE | in iris_upload_render_state()
7188 if (GEN_GEN == 9 && (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) { in iris_emit_raw_pipe_control()
7239 if (GEN_GEN < 11 && flags & PIPE_CONTROL_VF_CACHE_INVALIDATE) { in iris_emit_raw_pipe_control()
7526 (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE) ? "VF " : "", in iris_emit_raw_pipe_control()
7574 pc.VFCacheInvalidationEnable = flags & PIPE_CONTROL_VF_CACHE_INVALIDATE; in iris_emit_raw_pipe_control()
Diris_resource.c2154 flush |= PIPE_CONTROL_VF_CACHE_INVALIDATE; in iris_flush_bits_for_history()
/external/igt-gpu-tools/tests/
Dperf.c77 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1 << 4) macro