Searched refs:PhiReg (Results 1 – 5 of 5) sorted by relevance
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 1638 Register PhiReg = Phi->getOperand(i).getReg(); in fixupInductionVariable() local
1639 MachineInstr *DI = MRI->getVRegDef(PhiReg); in fixupInductionVariable()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 1599 unsigned PhiReg = Phi->getOperand(i).getReg(); in fixupInductionVariable() local
1600 MachineInstr *DI = MRI->getVRegDef(PhiReg); in fixupInductionVariable()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ModuloSchedule.cpp | 1651 Register PhiReg = MI.getOperand(0).getReg(); in moveStageBetweenBlocks() local
1654 MI.getOperand(0).setReg(PhiReg); in moveStageBetweenBlocks()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 3179 unsigned PhiReg, in emitLoadM0FromVGPRLoop() argument
3195 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg) in emitLoadM0FromVGPRLoop()
3280 unsigned PhiReg, in loadM0FromVGPR() argument
3311 InitResultReg, DstReg, PhiReg, TmpExec, in loadM0FromVGPR()
3442 Register PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in emitIndirectSrc() local
3447 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, in emitIndirectSrc()
3557 Register PhiReg = MRI.createVirtualRegister(VecRC); in emitIndirectDst() local
3559 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, in emitIndirectDst()
3565 .addReg(PhiReg, RegState::Undef, SubReg) // vdst in emitIndirectDst()
3568 .addReg(PhiReg, RegState::Implicit) in emitIndirectDst()
[all …]
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| D | AMDGPURegisterBankInfo.cpp | 764 Register PhiReg = MRI.createGenericVirtualRegister(ResTy); in executeInWaterfallLoop() local
766 PhiRegs.push_back(PhiReg); in executeInWaterfallLoop()
767 MRI.setRegBank(PhiReg, *DefBank); in executeInWaterfallLoop()
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