| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonEarlyIfConv.cpp | 125 : SplitB(B), TrueB(TB), FalseB(FB), JoinB(JB), PredR(PR) {} in FlowPattern()
131 unsigned PredR = 0; member
146 << ", PredR:" << printReg(P.FP.PredR, &P.TRI) in operator <<()
197 MachineInstr *MI, unsigned PredR, bool IfTrue);
200 unsigned PredR, bool IfTrue);
203 const TargetRegisterClass *DRC, unsigned PredR, unsigned TR,
253 Register PredR = T1I->getOperand(0).getReg(); in matchFlowPattern() local
334 FP = FlowPattern(B, PredR, TB, FB, JB); in matchFlowPattern()
711 unsigned PredR, bool IfTrue) { in predicateInstr() argument
729 MIB.addReg(PredR); in predicateInstr()
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| D | HexagonGenMux.cpp | 92 unsigned PredR = 0; member
108 unsigned DefR, PredR; member
115 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
256 if (F != CM.end() && F->second.PredR != PR) { in genMuxInBlock()
263 F->second.PredR = PR; in genMuxInBlock()
344 .addReg(MX.PredR) in genMuxInBlock()
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| D | HexagonExpandCondsets.cpp | 221 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
228 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
746 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) { in getReachingDefForPred() argument
759 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI))) in getReachingDefForPred()
769 if (RR.Reg == PredR) { in getReachingDefForPred()
909 unsigned PredR, bool Cond, MachineBasicBlock::iterator First, in renameInRange() argument
918 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI))) in renameInRange()
958 Register PredR = MP.getReg(); in predicate() local
959 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond); in predicate()
976 if (!I->modifiesRegister(PredR, nullptr)) in predicate()
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| D | HexagonHardwareLoops.cpp | 462 unsigned PredR, PredPos, PredRegFlags; in findInductionRegister() local
463 if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags)) in findInductionRegister()
466 MachineInstr *PredI = MRI->getVRegDef(PredR); in findInductionRegister()
1337 Register PredR = CmpI->getOperand(0).getReg(); in orderBumpCompare() local
1345 if (MO.getReg() == PredR) // Found an intervening use of PredR. in orderBumpCompare()
1915 Register PredR = PN->getOperand(i).getReg(); in createPreheaderForLoop() local
1921 MachineOperand MO = MachineOperand::CreateReg(PredR, false); in createPreheaderForLoop()
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| D | HexagonISelLowering.cpp | 347 Register PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); in LowerCallResult() local
348 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR, in LowerCallResult()
354 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1); in LowerCallResult()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonEarlyIfConv.cpp | 106 FlowPattern() : SplitB(0), TrueB(0), FalseB(0), JoinB(0), PredR(0) {} in FlowPattern()
109 : SplitB(B), TrueB(TB), FalseB(FB), JoinB(JB), PredR(PR) {} in FlowPattern()
113 unsigned PredR; member
126 << ", PredR:" << PrintReg(P.FP.PredR, &P.TRI) in operator <<()
174 MachineInstr *MI, unsigned PredR, bool IfTrue);
177 unsigned PredR, bool IfTrue);
227 unsigned PredR = T1I->getOperand(0).getReg(); in matchFlowPattern() local
306 FP = FlowPattern(B, PredR, TB, FB, JB); in matchFlowPattern()
708 unsigned PredR, bool IfTrue) { in predicateInstr() argument
721 .addReg(PredR); in predicateInstr()
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| D | HexagonGenMux.cpp | 62 unsigned PredR; member
64 CondsetInfo() : PredR(0), TrueX(UINT_MAX), FalseX(UINT_MAX) {} in CondsetInfo()
73 unsigned DefR, PredR; member
79 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
220 if (F != CM.end() && F->second.PredR != PR) { in genMuxInBlock()
227 F->second.PredR = PR; in genMuxInBlock()
300 .addReg(MX.PredR) in genMuxInBlock()
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| D | HexagonExpandCondsets.cpp | 258 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
265 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
743 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) { in getReachingDefForPred() argument
756 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI))) in getReachingDefForPred()
766 if (RR.Reg == PredR) { in getReachingDefForPred()
917 unsigned PredR, bool Cond, MachineBasicBlock::iterator First, in renameInRange() argument
926 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI))) in renameInRange()
967 unsigned PredR = MP.getReg(); in predicate() local
968 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond); in predicate()
985 if (!I->modifiesRegister(PredR, 0)) in predicate()
[all …]
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| D | HexagonHardwareLoops.cpp | 443 unsigned PredR, PredPos, PredRegFlags; in findInductionRegister() local
444 if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags)) in findInductionRegister()
447 MachineInstr *PredI = MRI->getVRegDef(PredR); in findInductionRegister()
1298 unsigned PredR = CmpI->getOperand(0).getReg(); in orderBumpCompare() local
1306 if (MO.getReg() == PredR) // Found an intervening use of PredR. in orderBumpCompare()
1877 unsigned PredR = PN->getOperand(i).getReg(); in createPreheaderForLoop() local
1883 MachineOperand MO = MachineOperand::CreateReg(PredR, false); in createPreheaderForLoop()
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| D | HexagonBitSimplify.cpp | 2692 unsigned PredR = 0; in processLoop() local
2693 if (!isSameShuffle(G.Out.Reg, G.Inp.Reg, F->PR.Reg, PredR)) { in processLoop()
2704 PredR = MRI->createVirtualRegister(RC); in processLoop()
2709 BuildMI(*C.PB, T, DL, HII->get(TfrI), PredR) in processLoop()
2712 PredR = F->PR.Reg; in processLoop()
2715 assert(MRI->getRegClass(PredR) == MRI->getRegClass(G.Inp.Reg)); in processLoop()
2716 moveGroup(G, *F->LB, *F->PB, F->LB->getFirstNonPHI(), F->DefR, PredR); in processLoop()
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| D | HexagonISelLowering.cpp | 636 unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); in LowerCallResult() local
637 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR, in LowerCallResult()
640 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1, in LowerCallResult()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineAndOrXor.cpp | 315 ICmpInst::Predicate &PredR) { in getMaskedTypeForICmpPair() argument
356 if (decomposeBitTestICmp(R1, R2, PredR, R11, R12, R2)) { in getMaskedTypeForICmpPair()
391 if (!ICmpInst::isEquality(PredR)) in getMaskedTypeForICmpPair()
433 unsigned RightType = getMaskedICmpType(A, D, E, PredR); in getMaskedTypeForICmpPair()
444 ICmpInst::Predicate PredL, ICmpInst::Predicate PredR, in foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed() argument
475 if (PredR != NewCC) in foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed()
574 ICmpInst::Predicate PredL, ICmpInst::Predicate PredR, in foldLogOpOfMaskedICmpsAsymmetric() argument
577 assert(ICmpInst::isEquality(PredL) && ICmpInst::isEquality(PredR) && in foldLogOpOfMaskedICmpsAsymmetric()
591 PredL, PredR, Builder)) { in foldLogOpOfMaskedICmpsAsymmetric()
597 PredR, PredL, Builder)) { in foldLogOpOfMaskedICmpsAsymmetric()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | EarlyCSE.cpp | 380 CmpInst::Predicate PredL, PredR; in isEqualImpl() local
383 match(CondR, m_Cmp(PredR, m_Specific(X), m_Specific(Y))) && in isEqualImpl()
384 CmpInst::getInversePredicate(PredL) == PredR) in isEqualImpl()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
| D | InstructionSimplify.cpp | 1804 FCmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate(); in simplifyAndOrOfFCmps() local
1805 if ((PredL == FCmpInst::FCMP_ORD && PredR == FCmpInst::FCMP_ORD && IsAnd) || in simplifyAndOrOfFCmps()
1806 (PredL == FCmpInst::FCMP_UNO && PredR == FCmpInst::FCMP_UNO && !IsAnd)) { in simplifyAndOrOfFCmps()
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