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/external/libxaac/decoder/armv7/
Dixheaacd_post_twiddle_overlap.s141 VMULL.S32 Q0, D2, D0
142 VQMOVN.S64 D8, Q0
189 VLD2.32 {Q0, Q1}, [R1], R12
193 VREV64.16 Q0, Q0
249 VMULL.U16 Q0, D26, D18
255 VSHR.U32 Q0, Q0, #16
257 VMLAL.S16 Q0, D27, D18
263 VADD.I32 Q14, Q14, Q0
266 VMULL.U16 Q0, D6, D9
270 VSHR.S32 Q0, Q0, #16
[all …]
Dia_xheaacd_mps_reoder_mulshift_acc.s45 VLD1.32 {Q0, Q1}, [R8]
47 VST1.32 {Q0, Q1}, [R7]
59 VLD1.32 {Q0, Q1}, [R8]! @LOADING values from R0 Sr_fix
69 VMULL.S32 Q0, D4, D12
74 VSHR.S64 Q0, Q0, #31
84 VSUB.I64 Q12, Q12, Q0
103 VLD1.32 {Q0, Q1}, [R8]! @LOADING values from R0 Sr_fix
113 VMULL.S32 Q0, D4, D12
123 VSHR.S64 Q0, Q0, #31
128 VSUB.I64 Q12, Q12, Q0
[all …]
Dixheaacd_post_twiddle.s157 VMULL.U16 Q0, D26, D10
173 VSHR.U32 Q0, Q0, #16
179 VMLAL.S16 Q0, D27, D10
187 VNEG.S32 Q0, Q0
189 VADD.I32 Q13, Q14, Q0
265 VMULL.U16 Q0, D26, D10
281 VSHR.U32 Q0, Q0, #16
287 VMLAL.S16 Q0, D27, D10
295 VNEG.S32 Q0, Q0
297 VADD.I32 Q13, Q14, Q0
[all …]
Dixheaacd_overlap_add1.s53 VQNEG.S32 Q0, Q3
96 VMULL.S32 Q0, D14, D4
97 VQMOVN.S64 D16, Q0
98 VMULL.S32 Q0, D15, D5
99 VQMOVN.S64 D17, Q0
102 VQNEG.S32 Q0, Q3
144 VMULL.S32 Q0, D4, D14
145 VQMOVN.S64 D16, Q0
146 VMULL.S32 Q0, D5, D15
147 VQMOVN.S64 D17, Q0
[all …]
Dixheaacd_dct3_32.s54 VLD1.32 {Q0}, [R6]!
62 VSHR.S32 Q0, Q0, #7
66 VADD.I32 Q2, Q1, Q0
81 VLD1.32 {Q0}, [R6]!
91 VSHR.S32 Q0, Q0, #7
104 VADD.I32 Q2, Q1, Q0
132 VLD1.32 {Q0}, [R6]!
141 VSHR.S32 Q0, Q0, #7
159 VADD.I32 Q2, Q1, Q0
195 VSHR.S32 Q0, Q0, #7
[all …]
Dixheaacd_no_lap1.s38 VQNEG.S32 Q0, Q0
42 VQSHL.S32 Q15, Q0, Q1
56 VQNEG.S32 Q0, Q0
63 VQSHL.S32 Q15, Q0, Q1
Dixheaacd_esbr_fwd_modulation.s41 VSHR.S32 Q0, Q0, #4
52 VQSUB.S32 Q4, Q0, Q2
55 VADD.S32 Q6, Q0, Q2
91 VADD.I64 Q0, Q2, Q5
94 VSHRN.I64 D0, Q0, #31
Dixheaacd_dec_DCT2_64_asm.s46 VLD2.32 {Q0, Q1}, [R0]!
49 VST1.32 {Q0}, [R1]!
86 VLD2.32 {Q0, Q1}, [R0]!
101 VSUB.I32 Q9, Q0, Q2
103 VADD.I32 Q8, Q0, Q2
116 VLD2.32 {Q0, Q1}, [R0]!
148 VSUB.I32 Q9, Q0, Q2
150 VADD.I32 Q8, Q0, Q2
161 VLD2.32 {Q0, Q1}, [R0]!
193 VSUB.I32 Q9, Q0, Q2
[all …]
Dixheaacd_esbr_cos_sin_mod_loop1.s58 VSHRN.I64 D0, Q0, #32
81 VADD.I64 Q0, Q5, Q2
84 VSHRN.I64 D0, Q0, #32
110 VSHRN.I64 D0, Q0, #32
133 VADD.I64 Q0, Q5, Q2
136 VSHRN.I64 D0, Q0, #32
Dixheaacd_calcmaxspectralline.s38 VABS.S32 Q0, Q0
44 VORR Q3, Q0, Q3
Dixheaacd_pre_twiddle_compute.s116 VREV64.16 Q0, Q0
178 VREV64.16 Q0, Q0
244 VREV64.16 Q0, Q0
326 VREV64.16 Q0, Q0
Dixheaacd_calc_post_twid.s66 VNEG.S32 Q0, Q0
/external/libhevc/common/arm/
Dihevc_resi_trans_32x32_a9q.s226 VADD.S16 Q0, Q4, Q5 @ ee[k] = e[k] + e[16-k] k->1-8 row 1
237 @ Q0 A1 A2 A3 A4 B1 B2 B3 B4
245 VADD.S16 Q13, Q0, Q4 @ eee[k] = ee[k] + ee[7 - k] row 1 & 2
247 VSUB.S16 Q0, Q0 ,Q4 @ eeo[k] = ee[k] - ee[7 - k] row 1 & 2 -- dual issue
403 VMULL.S16 Q0,D2,D4 @eo[4][0-3]* R1
404 VMLAL.S16 Q0,D3,D5 @eo[4][4-7]* R1
455 VTRN.32 Q0, Q5 @ R1
462 VADD.S32 Q0, Q0, Q5 @ R1 -- dual issue
467 VADD.S32 Q9, Q0, Q9 @ R1 -- dual issue
469 VMULL.S16 Q0,D12,D4 @o[0][0-3]* R1
[all …]
Dihevc_sao_edge_offset_class0.s190 VCLT.U8 Q0,Q13,Q14 @II vcltq_u8(pu1_cur_row, pu1_cur_row_tmp)
211 …VSUB.I8 Q10,Q0,Q15 @II sign_left = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_g…
215 VCLT.U8 Q0,Q13,Q14 @II vcltq_u8(pu1_cur_row, pu1_cur_row_tmp)
217 …VSUB.I8 Q11,Q0,Q15 @II sign_right = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_…
221 …VMOVL.U8 Q0,D26 @II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u…
245 …VADDW.S8 Q0,Q0,D30 @II pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val[…
248 …VMAX.S16 Q0,Q0,Q2 @II pi2_tmp_cur_row.val[0] = vmaxq_s16(pi2_tmp_cur_row.val…
251 …VMIN.U16 Q0,Q0,Q3 @II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u…
253 VMOVN.I16 D0,Q0 @II vmovn_s16(pi2_tmp_cur_row.val[0])
/external/llvm/test/CodeGen/ARM/
Dvldm-liveness.ll4 ; s1 = VLDRS [r0, 1], Q0<imp-def>
5 ; s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def>
6 ; s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def>
7 ; s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def>
11 ; imp-use of Q0, which is undefined.
D2010-06-29-PartialRedefFastAlloc.ll10 ; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial
11 ; redef, it cannot also get %Q0.
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonVectorPrint.cpp76 || (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
87 if (R >= Hexagon::Q0 && R <= Hexagon::Q3) { in getStringReg()
89 return S[R-Hexagon::Q0]; in getStringReg()
191 } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) { in runOnMachineFunction()
192 LLVM_DEBUG(dbgs() << "adding dump for Q" << Reg - Hexagon::Q0 << '\n'); in runOnMachineFunction()
/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td68 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
70 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
72 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
75 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
77 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
106 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
108 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
110 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
113 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
115 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
[all …]
/external/llvm/lib/Target/ARM/
DARMCallingConv.td75 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
82 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
83 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,
84 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,
94 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
138 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
139 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>,
141 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>,
142 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>
215 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td104 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
106 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
108 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
111 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
113 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
146 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
148 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
150 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
153 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
155 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
[all …]
/external/deqp-deps/glslang/Test/
Dhlsl.gs-hs-mix.tesc95 float4 Q0 = mul(proj_matrix, float4(P0, 1.0));
100 vertex.PositionCS = Q0;
116 vertex.PositionCS = Q0;
/external/angle/third_party/vulkan-deps/glslang/src/Test/
Dhlsl.gs-hs-mix.tesc95 float4 Q0 = mul(proj_matrix, float4(P0, 1.0));
100 vertex.PositionCS = Q0;
116 vertex.PositionCS = Q0;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallingConv.td77 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
84 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
85 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,
86 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,
97 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
142 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
143 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>,
145 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>,
146 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>
223 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
[all …]
/external/musl/src/math/
Dexpm1l.c68 Q0 = -9.516813471998079611319047060563358064497E4L, variable
106 qx = (((( x + Q4) * x + Q3) * x + Q2) * x + Q1) * x + Q0; in expm1l()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc271 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
284 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
297 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
316 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
333 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
515 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
528 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
541 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
560 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
576 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64…
[all …]

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