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Searched refs:Q31 (Results 1 – 17 of 17) sorted by relevance

/external/libxaac/decoder/
Dixheaacd_constants.h50 #define Q31 2147483647 macro
/external/llvm/lib/Target/AArch64/
DAArch64PBQPRegAlloc.cpp95 case AArch64::Q31: in isOdd()
DAArch64RegisterInfo.td386 def Q31 : AArch64Reg<31, "q31", [D31], ["v31", ""]>, DwarfRegAlias<B31>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64PBQPRegAlloc.cpp94 case AArch64::Q31: in isOdd()
DAArch64SchedPredicates.td201 CheckRegOperand<0, Q31>]>]>;
DAArch64RegisterInfo.td419 def Q31 : AArch64Reg<31, "q31", [D31], ["v31", ""]>, DwarfRegAlias<B31>;
780 def Z31 : AArch64Reg<31, "z31", [Q31, Z31_HI]>, DwarfRegNum<[127]>;
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp1258 case AArch64::Q30: Reg = AArch64::Q31; break; in getNextVectorRegister()
1260 case AArch64::Q31: in getNextVectorRegister()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCTargetDesc.cpp226 {codeview::RegisterId::ARM64_Q31, AArch64::Q31}, in initLLVMToCVRegMapping()
DAArch64InstPrinter.cpp1195 case AArch64::Q30: Reg = AArch64::Q31; break; in getNextVectorRegister()
1197 case AArch64::Q31: in getNextVectorRegister()
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp262 AArch64::Q30, AArch64::Q31
442 AArch64::Q30, AArch64::Q31
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp311 AArch64::Q30, AArch64::Q31
635 AArch64::Q30, AArch64::Q31
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenRegisterInfo.inc172 Q31 = 152,
2660 … AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31,
3933 { AArch64::Q31, 95U },
4212 { AArch64::Q31, 95U },
20422 …ch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
20424 …ch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
20446 …ch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
20448 …ch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
20450 …ch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
DAArch64GenSubtargetInfo.inc14046 || MI->getOperand(0).getReg() == AArch64::Q31
14200 || MI->getOperand(0).getReg() == AArch64::Q31
14354 || MI->getOperand(0).getReg() == AArch64::Q31
14565 || MI->getOperand(0).getReg() == AArch64::Q31
14606 || MI->getOperand(0).getReg() == AArch64::Q31
16575 || MI->getOperand(0).getReg() == AArch64::Q31
16616 || MI->getOperand(0).getReg() == AArch64::Q31
19682 || MI->getOperand(0).getReg() == AArch64::Q31
19836 || MI->getOperand(0).getReg() == AArch64::Q31
19990 || MI->getOperand(0).getReg() == AArch64::Q31
[all …]
DAArch64GenAsmMatcher.inc11456 case AArch64::Q31: OpKind = MCK_FPR128; break;
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp1888 .Case("v31", AArch64::Q31) in matchVectorRegName()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp2121 .Case("v31", AArch64::Q31) in MatchNeonVectorRegName()
/external/llvm/docs/
DLangRef.rst3584 128 or 256-bit QPX register (``Q0-Q31``; aliases the ``F`` registers).
3586 128 or 256-bit QPX register (``Q0-Q31``), otherwise a 128-bit