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Searched refs:RB0 (Results 1 – 5 of 5) sorted by relevance

/external/clang/test/Layout/
Dms-x86-pack-and-align.cpp416 struct __declspec(align(8)) RB0 { struct
794 sizeof(RB0)+
/external/rust/crates/libm/src/math/
Derff.rs71 const RB0: f32 = -9.8649431020e-03; /* 0xbc21a092 */ constant
118 r = RB0 + s * (RB1 + s * (RB2 + s * (RB3 + s * (RB4 + s * (RB5 + s * RB6))))); in erfc2()
Derf.rs160 const RB0: f64 = -9.86494292470009928597e-03; /* 0xBF843412, 0x39E86F4A */ constant
208 r = RB0 + s * (RB1 + s * (RB2 + s * (RB3 + s * (RB4 + s * (RB5 + s * RB6))))); in erfc2()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPURegisterBankInfo.cpp2398 static unsigned regBankUnion(unsigned RB0, unsigned RB1) { in regBankUnion() argument
2399 return (RB0 == AMDGPU::SGPRRegBankID && RB1 == AMDGPU::SGPRRegBankID) ? in regBankUnion()
2403 static int regBankBoolUnion(int RB0, int RB1) { in regBankBoolUnion() argument
2404 if (RB0 == -1) in regBankBoolUnion()
2407 return RB0; in regBankBoolUnion()
2412 if (RB0 == AMDGPU::VCCRegBankID || RB1 == AMDGPU::VCCRegBankID) in regBankBoolUnion()
2416 return regBankUnion(RB0, RB1); in regBankBoolUnion()
/external/OpenCSD/decoder/tests/snapshots-ete/ts_bit64_set/bindir_64/
DVAL_TEST_CODE_exec327 �� �� @������_������ �����RB0����*�� qIJ� *