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Searched refs:RL (Results 1 – 25 of 156) sorted by relevance

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/external/cldr/tools/cldr-code/src/main/resources/org/unicode/cldr/util/data/external/
D2013-1_UNLOCODE_CodeListPart3.csv2 "+","OM","ALA","Al Azaiba","Al Azaiba","MA","--3-----","RL","1301",,"2336S 05832E",
5 ,"OM","DQM","Duqm","Duqm","WU","1-3-----","RL","1207",,"1939N 05742E",
6 ,"OM","FAH","Fahal","Fahal","MA","1-------","RL","0212",,"2341N 05830E",
10 ,"OM","MFH","Mina' al Fahl","Mina' al Fahl","MA","1-------","RL","0212",,"2338N 05831E",
11 ,"OM","MNQ","Mina' Qabus","Mina' Qabus","MA","--3-----","RL","0212",,"2337N 05834E",
12 ,"OM","STQ","Mina Sultan Qaboos, Muscat","Mina Sultan Qaboos, Muscat",,"1-3-----","RL","0607",,"233…
17 ,"OM","QAL","Qalhat","Qalhat","SH","1-3-----","RL","0307",,"2242N 05922E",
20 ,"OM","RUS","Rusayl","Rusayl","MA","--3-----","RL","0701",,"2332N 05811E",
23 ,"OM","SEE","Seeb","Seeb",,"--3-----","RL","0201",,"2335N 05817E",
29 ,"PA","ABA","Agua Buena","Agua Buena",,"--3--6--","RL","0607",,"0735N 08017W",
[all …]
D2013-1_UNLOCODE_CodeListPart1.csv3 ,"AD","CAN","Canillo","Canillo",,"--3-----","RL","0307",,"4234N 00135E",
4 ,"AD","ENC","Encamp","Encamp",,"--3-----","RL","0307",,"4232N 00134E",
5 ,"AD","ESC","Escaldes-Engordany","Escaldes-Engordany",,"--3-----","RL","0307",,"4231N 00133E",
7 ,"AD","LMA","La Massana","La Massana",,"--3-----","RL","0307",,"4234N 00129E",
8 ,"AD","ORD","Ordino","Ordino",,"--3-----","RL","0307",,"4233N 00131E",
9 ,"AD","PAS","Pas de la Casa","Pas de la Casa",,"--3----B","RL","0307",,"4233N 00144E",
10 ,"AD","SJL","Sant Juli� de L�ria","Sant Julia de Loria",,"--3-----","RL","1101",,"4228N 00130E",""
11 ,"AD","SCO","Santa Coloma","Santa Coloma",,"--3-----","RL","0307",,"4230N 00130E",
13 ,"AE","ABU","Abu al Bukhoosh","Abu al Bukhoosh",,"1-------","RL","0307",,"2529N 05308E",
15 ,"AE","AMU","Abu Musa","Abu Musa",,"1-------","RL","0201",,"2552N 05501E",
[all …]
D2013-1_UNLOCODE_CodeListPart2.csv4 ,"GA","BEL","Belleville","Belleville",,"--3-----","RL","0607",,"0002N 01102E",
10 ,"GA","CCB","Cocobeach","Cocobeach",,"1-------","RL","9811",,,
11 ,"GA","EKU","Equata","Equata","1","1-------","RL","0212",,"0013S 00918E",
18 ,"GA","KOU","Koulamoutou","Koulamoutou",,"--34----","RL","0212",,"0107S 01230E",
28 ,"GA","MBA","Mayumba","Mayumba","05","-----6--","RL","0901",,"0259N 01017E",
40 ,"GA","MVE","Mvengu�","Mvengue",,"--3-----","RL","0201",,"0139S 01323E",
45 ,"GA","OGU","Oguandjo Terminal","Oguandjo Terminal",,"1-------","RL","0901",,"0130S 00854E",
56 ,"GA","WNE","Wora Na Ye","Wora Na Ye",,"--34----","RL","0907",,"0221S 00920E",
58 ,"GB","BYS","Abbeystead","Abbeystead","LAN","-----6--","RL","1201",,"5358N 00240W",
59 ,"GB","ASB","Abbots Bromley","Abbots Bromley","STS","--3-----","RL","0201",,"5249N 00153W",
[all …]
/external/compiler-rt/test/tsan/
Ddeadlock_detector_stress_test.cc129 void RL(size_t i) { in RL() function in LockTest
284 RL(0); L(1); RU(0); U(1); in Test8()
285 L(1); RL(0); RU(0); U(1); in Test8()
290 RL(2); RL(3); RU(2); RU(3); in Test8()
291 RL(3); RL(2); RU(2); RU(3); in Test8()
374 RL(000); in Test12_Thread()
375 RL(100); in Test12_Thread()
376 RL(200); in Test12_Thread()
377 RL(300); in Test12_Thread()
397 RL(0); in Test13_Thread()
[all …]
/external/tensorflow/tensorflow/python/debug/cli/
Dcurses_widgets.py19 RL = debugger_cli_common.RichLine variable
173 output = RL("| ")
174 output += RL(
178 output += RL(" ")
179 output += RL(
188 output += RL(" | ")
190 output += RL("(-%d) " % (len(self._items) - 1 - self._pointer),
196 output += RL(maybe_truncated_command, command_attribute)
Dprofile_analyzer_cli.py30 RL = debugger_cli_common.RichLine variable
127 return RL(text, font_attr=menu_item)
530 output = [RL("-" * screen_cols)]
533 output.append(RL(device_row))
534 output.append(RL())
538 row = RL()
546 row += RL(column_name, font_attr=[head_menu_item, "bold"])
547 row += RL(" " * (column_widths[col] - len(column_name)))
553 new_row = RL()
562 new_row += RL(" " * (column_widths[col] - len(new_cell)))
[all …]
Dcli_config.py23 RL = debugger_cli_common.RichLine variable
135 lines = [RL("Command-line configuration:", "bold"), RL("")]
138 line = RL(" ")
139 line += RL(name, ["underline", highlight_attr])
140 line += RL(": ")
141 line += RL(str(val), font_attr=highlight_attr)
Danalyzer_cli.py34 RL = debugger_cli_common.RichLine variable
846 lines = [RL(""), RL(""), RL("Traceback of node construction:", "bold")]
856 line_number_line = RL(" ")
857 line_number_line += RL("Line: %d" % line, attribute)
1124 annotated_line = RL("L%d" % (i + 1), cli_shared.COLOR_YELLOW)
1136 omitted_info_line = RL(" (... Omitted %d of %d %s ...) " % (
1140 omitted_info_line += RL(
1149 label = RL(" " * 4)
1156 label += RL(element, attribute)
1188 lines = [RL("TensorFlow Python library file(s):", color)]
[all …]
Dcli_shared.py28 RL = debugger_cli_common.RichLine variable
225 RL("ERROR: " + msg, COLOR_RED)])
250 lines = [RL(indent_str) + RL(command, font_attr) + ":",
358 more_lines.append(RL(" * ") + RL(filter_name, command_menu_node))
367 out.append_rich_line(RL("For more details, see ") +
368 RL("help.", debugger_cli_common.MenuItem("", "help")) +
447 RL("!!! An error occurred during the run !!!", "blink"),
/external/clang/lib/StaticAnalyzer/Checkers/
DPaddingChecker.cpp79 const ASTRecordLayout &RL = ASTContext.getASTRecordLayout(RD); in visitRecord() local
80 assert(llvm::isPowerOf2_64(RL.getAlignment().getQuantity())); in visitRecord()
82 CharUnits BaselinePad = calculateBaselinePad(RD, ASTContext, RL); in visitRecord()
85 CharUnits OptimalPad = calculateOptimalPad(RD, ASTContext, RL); in visitRecord()
168 const ASTRecordLayout &RL) { in calculateBaselinePad() argument
170 CharUnits Offset = ASTContext.toCharUnitsFromBits(RL.getFieldOffset(0)); in calculateBaselinePad()
177 auto FieldOffsetBits = RL.getFieldOffset(FD->getFieldIndex()); in calculateBaselinePad()
182 PaddingSum += RL.getSize() - Offset; in calculateBaselinePad()
204 const ASTRecordLayout &RL) { in calculateOptimalPad() argument
234 CharUnits NewOffset = ASTContext.toCharUnitsFromBits(RL.getFieldOffset(0)); in calculateOptimalPad()
[all …]
/external/llvm/test/CodeGen/Generic/
Di128-addsub.ll3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
15 store i64 %tmp1617, i64* %RL
22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
34 store i64 %tmp1617, i64* %RL
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Remarks/
DYAMLRemarkSerializer.cpp24 Optional<RemarkLocation> RL, T FunctionName, in mapRemarkHeader() argument
29 io.mapOptional("DebugLoc", RL); in mapRemarkHeader()
77 static void mapping(IO &io, RemarkLocation &RL) { in mapping()
80 StringRef File = RL.SourceFilePath; in mapping()
81 unsigned Line = RL.SourceLine; in mapping()
82 unsigned Col = RL.SourceColumn; in mapping()
/external/llvm/lib/Target/Hexagon/
DHexagonBlockRanges.cpp74 void HexagonBlockRanges::RangeList::include(const RangeList &RL) { in include() argument
75 for (auto &R : RL) in include()
389 RangeList &RL = F->second; in computeDeadMap() local
390 RangeList::iterator A = RL.begin(), Z = RL.end()-1; in computeDeadMap()
461 const HexagonBlockRanges::RangeList &RL) { in operator <<() argument
462 for (auto &R : RL) in operator <<()
479 const HexagonBlockRanges::RangeList &RL = I.second; in operator <<() local
480 OS << PrintReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n"; in operator <<()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonBlockRanges.cpp75 void HexagonBlockRanges::RangeList::include(const RangeList &RL) { in include() argument
76 for (auto &R : RL) in include()
442 RangeList &RL = F->second; in computeDeadMap() local
443 RangeList::iterator A = RL.begin(), Z = RL.end()-1; in computeDeadMap()
514 const HexagonBlockRanges::RangeList &RL) { in operator <<() argument
515 for (auto &R : RL) in operator <<()
532 const HexagonBlockRanges::RangeList &RL = I.second; in operator <<() local
533 OS << printReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n"; in operator <<()
/external/clang/lib/CodeGen/
DCGRecordLayoutBuilder.cpp713 CGRecordLayout *RL = in ComputeRecordLayout() local
717 RL->NonVirtualBases.swap(Builder.NonVirtualBases); in ComputeRecordLayout()
718 RL->CompleteObjectVirtualBases.swap(Builder.VirtualBases); in ComputeRecordLayout()
721 RL->FieldInfo.swap(Builder.Fields); in ComputeRecordLayout()
724 RL->BitFields.swap(Builder.BitFields); in ComputeRecordLayout()
732 RL->print(llvm::outs()); in ComputeRecordLayout()
756 dyn_cast<llvm::StructType>(RL->getLLVMType()); in ComputeRecordLayout()
767 unsigned FieldNo = RL->getLLVMFieldNo(FD); in ComputeRecordLayout()
781 const CGBitFieldInfo &Info = RL->getBitFieldInfo(FD); in ComputeRecordLayout()
782 llvm::Type *ElementTy = ST->getTypeAtIndex(RL->getLLVMFieldNo(FD)); in ComputeRecordLayout()
[all …]
DCGObjCRuntime.cpp41 const ASTRecordLayout *RL; in LookupFieldBitOffset() local
43 RL = &CGM.getContext().getASTObjCImplementationLayout(ID); in LookupFieldBitOffset()
45 RL = &CGM.getContext().getASTObjCInterfaceLayout(Container); in LookupFieldBitOffset()
60 assert(Index < RL->getFieldCount() && "Ivar is not inside record layout!"); in LookupFieldBitOffset()
62 return RL->getFieldOffset(Index); in LookupFieldBitOffset()
/external/openthread/third_party/mbedtls/repo/library/
DMakefile55 RL ?= ranlib macro
208 $(RL) $(RLFLAGS) $@
235 $(RL) $(RLFLAGS) $@
262 $(RL) $(RLFLAGS) $@
/external/llvm/test/CodeGen/Hexagon/
Dsube.ll12 define void @check_sube_subc(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
24 store i64 %tmp1617, i64* %RL
Dadde.ll17 define void @check_adde_addc (i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
29 store i64 %tmp1617, i64* %RL
/external/walt/hardware/
DWALT_bom_r07.tsv7 R7,R5 2 Resistor (100) 100 Ohm SMD 0603 (1608 metric) Yageo RC0603FR-07100RL
10 R2,R1 2 Resistor (330R) 330 Ohm SMD 0603 (1608 metric) Yageo RC0603JR-07330RL
DWALT_bom_r09.tsv7 R7,R5, R8 3 Resistor (100) 100 Ohm SMD 0603 (1608 metric) Yageo RC0603FR-07100RL
10 R2,R1 2 Resistor (330R) 330 Ohm SMD 0603 (1608 metric) Yageo RC0603JR-07330RL
/external/mbedtls/library/
DMakefile63 RL ?= ranlib macro
222 $(RL) $(RLFLAGS) $@
251 $(RL) $(RLFLAGS) $@
280 $(RL) $(RLFLAGS) $@
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyExplicitLocals.cpp379 auto RL = Reg2Local.find(Reg); in runOnMachineFunction() local
380 if (RL == Reg2Local.end() || RL->second < MFI.getParams().size()) in runOnMachineFunction()
383 MFI.setLocal(RL->second - MFI.getParams().size(), in runOnMachineFunction()
/external/llvm/lib/Target/NVPTX/
DNVPTXRegisterInfo.td38 def RL#i : NVPTXReg<"%rd"#i>; // 64-bit
59 def Int64Regs : NVPTXRegClass<[i64], 64, (add (sequence "RL%u", 0, 4))>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypesGeneric.cpp506 SDValue LL, LH, RL, RH, CL, CH; in SplitRes_SELECT() local
509 GetSplitOp(N->getOperand(2), RL, RH); in SplitRes_SELECT()
538 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), CL, LL, RL); in SplitRes_SELECT()
544 SDValue LL, LH, RL, RH; in SplitRes_SELECT_CC() local
547 GetSplitOp(N->getOperand(3), RL, RH); in SplitRes_SELECT_CC()
550 N->getOperand(1), LL, RL, N->getOperand(4)); in SplitRes_SELECT_CC()

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