| /external/oboe/samples/RhythmGame/third_party/glm/simd/ |
| D | integer.h | 17 glm_uvec4 Reg2; in glm_i128_interleave() local
26 Reg2 = _mm_slli_si128(Reg1, 2); in glm_i128_interleave()
27 Reg1 = _mm_or_si128(Reg2, Reg1); in glm_i128_interleave()
32 Reg2 = _mm_slli_si128(Reg1, 1); in glm_i128_interleave()
33 Reg1 = _mm_or_si128(Reg2, Reg1); in glm_i128_interleave()
38 Reg2 = _mm_slli_epi32(Reg1, 4); in glm_i128_interleave()
39 Reg1 = _mm_or_si128(Reg2, Reg1); in glm_i128_interleave()
44 Reg2 = _mm_slli_epi32(Reg1, 2); in glm_i128_interleave()
45 Reg1 = _mm_or_si128(Reg2, Reg1); in glm_i128_interleave()
50 Reg2 = _mm_slli_epi32(Reg1, 1); in glm_i128_interleave()
[all …]
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 454 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true); in generateCompactUnwindEncoding() local
465 Reg2 = getXRegFromWReg(Reg2); in generateCompactUnwindEncoding()
467 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
470 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
473 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
476 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
479 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
484 Reg2 = getDRegFromBReg(Reg2); in generateCompactUnwindEncoding()
490 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
493 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 640 unsigned Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true); in generateCompactUnwindEncoding() local
651 Reg2 = getXRegFromWReg(Reg2); in generateCompactUnwindEncoding()
653 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
656 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
659 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
662 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
665 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
670 Reg2 = getDRegFromBReg(Reg2); in generateCompactUnwindEncoding()
676 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
679 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 874 RegPairInfo() : Reg1(AArch64::NoRegister), Reg2(AArch64::NoRegister) {} in RegPairInfo()
876 unsigned Reg2; member
880 bool isPaired() const { return Reg2 != AArch64::NoRegister; } in isPaired()
916 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
934 ((RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) || in computeCalleeSaveRegisterPairs()
935 RPI.Reg1 + 1 == RPI.Reg2))) && in computeCalleeSaveRegisterPairs()
975 unsigned Reg2 = RPI.Reg2; in spillCalleeSavedRegisters() local
994 dbgs() << ", " << TRI->getName(Reg2); in spillCalleeSavedRegisters()
1003 MBB.addLiveIn(Reg2); in spillCalleeSavedRegisters()
1004 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2)); in spillCalleeSavedRegisters()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 1867 static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateWindowsRegisterPairing() argument
1877 if (Reg2 == AArch64::FP) in invalidateWindowsRegisterPairing()
1881 if (Reg2 == Reg1 + 1) in invalidateWindowsRegisterPairing()
1890 static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateRegisterPairing() argument
1893 return invalidateWindowsRegisterPairing(Reg1, Reg2, NeedsWinCFI); in invalidateRegisterPairing()
1898 return Reg2 == AArch64::LR; in invalidateRegisterPairing()
1907 unsigned Reg2 = AArch64::NoRegister; member
1914 bool isPaired() const { return Reg2 != AArch64::NoRegister; } in isPaired()
1988 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
1993 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.h | 73 unsigned Reg1, unsigned Reg2);
76 unsigned Reg1, unsigned Reg2, unsigned Reg3);
79 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
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| D | MipsAsmPrinter.cpp | 770 unsigned Reg2) { in EmitInstrRegReg() argument
779 Reg1 = Reg2; in EmitInstrRegReg()
780 Reg2 = Temp; in EmitInstrRegReg()
784 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegReg()
790 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
794 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegRegReg()
801 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair() argument
805 Reg1 = Reg2; in EmitMovFPIntPair()
806 Reg2 = temp; in EmitMovFPIntPair()
809 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
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| D | Mips16InstrInfo.h | 115 unsigned Reg1, unsigned Reg2) const;
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| D | Mips16InstrInfo.cpp | 263 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
274 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); in adjustStackPtrBig()
278 MIB3.addReg(Reg2, RegState::Kill); in adjustStackPtrBig()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.h | 94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
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| D | MipsAsmPrinter.cpp | 876 unsigned Reg2) { in EmitInstrRegReg() argument
885 Reg1 = Reg2; in EmitInstrRegReg()
886 Reg2 = Temp; in EmitInstrRegReg()
890 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegReg()
896 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
900 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegRegReg()
907 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair() argument
911 Reg1 = Reg2; in EmitMovFPIntPair()
912 Reg2 = temp; in EmitMovFPIntPair()
915 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
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| D | MicroMipsSizeReduction.cpp | 378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
388 if (Registers[i + 1] == Reg2) in ConsecutiveRegisters()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr() local
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP() local
481 if (Reg1 != Reg2) in ReduceXWtoXWP()
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| D | Mips16InstrInfo.cpp | 278 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
289 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); in adjustStackPtrBig()
293 MIB3.addReg(Reg2, RegState::Kill); in adjustStackPtrBig()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 420 bool &HaveReg2, Register &Reg2,
836 bool &HaveReg2, Register &Reg2, in parseAddress() argument
865 if (parseRegister(Reg2)) in parseAddress()
900 Register Reg1, Reg2; in parseAddress() local
904 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length)) in parseAddress()
939 if (parseAddressRegister(Reg2)) in parseAddress()
941 Base = Regs[Reg2.Num]; in parseAddress()
952 if (parseAddressRegister(Reg2)) in parseAddress()
954 Base = Regs[Reg2.Num]; in parseAddress()
976 if (parseAddressRegister(Reg2)) in parseAddress()
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | newvaluejump2.ll | 10 %Reg2 = alloca i32, align 4
11 %0 = load i32, i32* %Reg2, align 4
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 188 unsigned Reg2,
403 unsigned Reg2, in getOperandGatherWeight() argument
417 if (Def->modifiesRegister(Reg2, TRI)) in getOperandGatherWeight()
541 unsigned Reg2 = OperandMasks[J].Reg; in collectCandidates() local
550 " and " << printReg(Reg2, SubReg2) << '\n'); in collectCandidates()
552 unsigned Weight = getOperandGatherWeight(MI, Reg1, Reg2, StallCycles); in collectCandidates()
558 unsigned FreeBanks2 = getFreeBanks(Reg2, SubReg2, Mask2, UsedBanks); in collectCandidates()
563 Candidates.push(Candidate(&MI, Reg2, FreeBanks2, Weight in collectCandidates()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 189 unsigned Reg2 = MI->getOperand(2).getReg(); in processBlock() local
191 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
192 && Reg2 != OldFMAReg) { in processBlock()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock() local
192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
193 && Reg2 != OldFMAReg) { in processBlock()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 145 unsigned Reg2, bool isKill2) { in addRegReg() argument
147 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 166 unsigned Reg2, bool isKill2) { in addRegReg() argument
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 98 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
102 !Register::isPhysicalRegister(Reg2)) in contains()
104 return MC->contains(Reg1, Reg2); in contains()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 710 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
713 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
715 if (Reg0 != Reg2) { in ReduceTo2Addr()
745 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
746 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.h | 100 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 176 Register Reg2 = MI.getOperand(Idx2).getReg(); in commuteInstructionImpl() local
191 bool Reg2IsRenamable = Register::isPhysicalRegister(Reg2) in commuteInstructionImpl()
199 Reg0 = Reg2; in commuteInstructionImpl()
201 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
222 CommutedMI->getOperand(Idx1).setReg(Reg2); in commuteInstructionImpl()
235 if (Register::isPhysicalRegister(Reg2)) in commuteInstructionImpl()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1386 StringRef Reg2(R2); in processInstruction() local
1387 Inst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
1401 StringRef Reg2(R2); in processInstruction() local
1402 Inst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
1417 StringRef Reg2(R2); in processInstruction() local
1418 Inst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
1749 StringRef Reg2(R2); in processInstruction() local
1753 TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
1893 StringRef Reg2(R2); in processInstruction() local
1897 TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
|