| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 434 bool isSubRegister(unsigned RegA, unsigned RegB) const { in isSubRegister() argument
435 return isSuperRegister(RegB, RegA); in isSubRegister()
439 bool isSuperRegister(unsigned RegA, unsigned RegB) const;
442 bool isSubRegisterEq(unsigned RegA, unsigned RegB) const { in isSubRegisterEq() argument
443 return isSuperRegisterEq(RegB, RegA); in isSubRegisterEq()
448 bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const { in isSuperRegisterEq() argument
449 return RegA == RegB || isSuperRegister(RegA, RegB); in isSuperRegisterEq()
454 bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const { in isSuperOrSubRegisterEq() argument
455 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB); in isSuperOrSubRegisterEq()
527 inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{ in isSuperRegister() argument
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 553 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { in isSubRegister() argument
554 return isSuperRegister(RegB, RegA); in isSubRegister()
558 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const;
561 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSubRegisterEq() argument
562 return isSuperRegisterEq(RegB, RegA); in isSubRegisterEq()
567 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperRegisterEq() argument
568 return RegA == RegB || isSuperRegister(RegA, RegB); in isSuperRegisterEq()
573 bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperOrSubRegisterEq() argument
574 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB); in isSuperOrSubRegisterEq()
649 inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) const{ in isSuperRegister() argument
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| /external/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 115 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
119 unsigned RegA, unsigned RegB, unsigned Dist);
534 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { in regsAreCompatible() argument
535 if (RegA == RegB) in regsAreCompatible()
537 if (!RegA || !RegB) in regsAreCompatible()
539 return TRI->regsOverlap(RegA, RegB); in regsAreCompatible()
664 unsigned RegA = MI->getOperand(0).getReg(); in commuteInstruction() local
665 SrcRegMap[RegA] = FromRegC; in commuteInstruction()
674 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){ in isProfitableToConv3Addr() argument
684 unsigned ToRegA = getMappedReg(RegA, DstRegMap); in isProfitableToConv3Addr()
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| D | TargetInstrInfo.cpp | 701 unsigned RegA = OpA.getReg(); in reassociateOps() local
707 if (TargetRegisterInfo::isVirtualRegister(RegA)) in reassociateOps()
708 MRI.constrainRegClass(RegA, RC); in reassociateOps()
736 .addReg(RegA, getKillRegState(KillA)) in reassociateOps()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 139 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
143 unsigned RegA, unsigned RegB, unsigned Dist);
561 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { in regsAreCompatible() argument
562 if (RegA == RegB) in regsAreCompatible()
564 if (!RegA || !RegB) in regsAreCompatible()
566 return TRI->regsOverlap(RegA, RegB); in regsAreCompatible()
702 Register RegA = MI->getOperand(DstIdx).getReg(); in commuteInstruction() local
703 SrcRegMap[RegA] = FromRegC; in commuteInstruction()
712 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){ in isProfitableToConv3Addr() argument
722 unsigned ToRegA = getMappedReg(RegA, DstRegMap); in isProfitableToConv3Addr()
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| D | ImplicitNullChecks.cpp | 282 Register RegA = MOA.getReg(); in canReorder() local
289 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef())) in canReorder()
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| D | TargetInstrInfo.cpp | 809 Register RegA = OpA.getReg(); in reassociateOps() local
815 if (Register::isVirtualRegister(RegA)) in reassociateOps()
816 MRI.constrainRegClass(RegA, RC); in reassociateOps()
844 .addReg(RegA, getKillRegState(KillA)) in reassociateOps()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86WinAllocaExpander.cpp | 219 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower() local
221 .addReg(RegA, RegState::Undef); in lower()
233 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower() local
235 .addReg(RegA, RegState::Undef); in lower()
247 unsigned RegA = Is64BitAlloca ? X86::RAX : X86::EAX; in lower() local
248 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY), RegA) in lower()
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| /external/llvm/lib/Target/X86/ |
| D | X86WinAllocaExpander.cpp | 214 unsigned RegA = (SlotSize == 8) ? X86::RAX : X86::EAX; in lower() local
222 .addReg(RegA, RegState::Undef); in lower()
233 .addReg(RegA, RegState::Undef); in lower()
243 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY), RegA) in lower()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1980 for (auto &RegA : DefsA) in isDependent() local
1983 if (RegA == RegB) in isDependent()
1986 if (Hexagon::DoubleRegsRegClass.contains(RegA)) in isDependent()
1987 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent()
1993 if (RegA == *SubRegs) in isDependent()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 2102 for (auto &RegA : DefsA) in isDependent() local
2105 if (RegA == RegB) in isDependent()
2108 if (Register::isPhysicalRegister(RegA)) in isDependent()
2109 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent()
2115 if (RegA == *SubRegs) in isDependent()
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