| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.cpp | 1017 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex, in calculateIndirectAddress() argument
1020 return RegIndex; in calculateIndirectAddress()
1037 unsigned RegIndex = MI.getOperand(RegOpIdx).getImm(); in expandPostRAPseudo() local
1039 unsigned Address = calculateIndirectAddress(RegIndex, Channel); in expandPostRAPseudo()
1051 unsigned RegIndex = MI.getOperand(RegOpIdx).getImm(); in expandPostRAPseudo() local
1053 unsigned Address = calculateIndirectAddress(RegIndex, Channel); in expandPostRAPseudo()
1060 calculateIndirectAddress(RegIndex, Channel), in expandPostRAPseudo()
1198 unsigned RegIndex; in getIndirectIndexBegin() local
1200 for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd; in getIndirectIndexBegin()
1201 ++RegIndex) { in getIndirectIndexBegin()
[all …]
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| D | R600InstrInfo.h | 226 unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.cpp | 1036 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex, in calculateIndirectAddress() argument
1039 return RegIndex; in calculateIndirectAddress()
1056 unsigned RegIndex = MI.getOperand(RegOpIdx).getImm(); in expandPostRAPseudo() local
1058 unsigned Address = calculateIndirectAddress(RegIndex, Channel); in expandPostRAPseudo()
1070 unsigned RegIndex = MI.getOperand(RegOpIdx).getImm(); in expandPostRAPseudo() local
1072 unsigned Address = calculateIndirectAddress(RegIndex, Channel); in expandPostRAPseudo()
1079 calculateIndirectAddress(RegIndex, Channel), in expandPostRAPseudo()
1221 unsigned RegIndex; in getIndirectIndexBegin() local
1223 for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd; in getIndirectIndexBegin()
1224 ++RegIndex) { in getIndirectIndexBegin()
[all …]
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| D | R600InstrInfo.h | 225 unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const;
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLowering.cpp | 184 for (int32_t RegIndex = 0; RegIndex < NumRegs; ++RegIndex) { in filterTypeToRegisterSet() local
185 const auto RegNum = RegNumT::fromInt(RegIndex); in filterTypeToRegisterSet()
206 const int32_t RegIndex = RegNameToIndex.at(RName); in filterTypeToRegisterSet() local
211 RegSet[TypeIndex][RegIndex] = TypeToRegisterSet[TypeIndex][RegIndex]; in filterTypeToRegisterSet()
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| D | IceTargetLoweringARM32.cpp | 6098 Variable *RegIndex = nullptr; in legalize() local
6106 RegIndex = legalizeToReg(Index); in legalize()
6118 if (Base != RegBase || Index != RegIndex) { in legalize()
6121 if (RegIndex) { in legalize()
6122 Mem = OperandARM32Mem::create(Func, Ty, RegBase, RegIndex, in legalize()
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| D | IceTargetLoweringX8664.cpp | 6622 Variable *RegIndex = nullptr; in legalize() local
6631 RegIndex = llvm::cast<Variable>( in legalize()
6635 if (Base != RegBase || Index != RegIndex) { in legalize()
6636 Mem = X86OperandMem::create(Func, Ty, RegBase, Offset, RegIndex, Shift, in legalize()
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| D | IceTargetLoweringX8632.cpp | 7360 Variable *RegIndex = nullptr; in legalize() local
7369 RegIndex = llvm::cast<Variable>( in legalize()
7373 if (Base != RegBase || Index != RegIndex) { in legalize()
7374 Mem = X86OperandMem::create(Func, Ty, RegBase, Offset, RegIndex, Shift, in legalize()
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| /external/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 1168 SlotIndex RegIndex = Idx.getRegSlot(); in eliminateUndefCopy() local
1171 VNInfo *VNI = DstLI.getVNInfoAt(RegIndex); in eliminateUndefCopy()
1180 VNInfo *SVNI = SR.getVNInfoAt(RegIndex); in eliminateUndefCopy()
1181 assert(SVNI != nullptr && SlotIndex::isSameInstr(SVNI->def, RegIndex)); in eliminateUndefCopy()
1186 LIS->removeVRegDefAt(DstLI, RegIndex); in eliminateUndefCopy()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 1576 SlotIndex RegIndex = Idx.getRegSlot(); in eliminateUndefCopy() local
1577 LiveRange::Segment *Seg = DstLI.getSegmentContaining(RegIndex); in eliminateUndefCopy()
1598 VNInfo *VNI = DstLI.getVNInfoAt(RegIndex); in eliminateUndefCopy()
1607 VNInfo *SVNI = SR.getVNInfoAt(RegIndex); in eliminateUndefCopy()
1608 assert(SVNI != nullptr && SlotIndex::isSameInstr(SVNI->def, RegIndex)); in eliminateUndefCopy()
1613 LIS->removeVRegDefAt(DstLI, RegIndex); in eliminateUndefCopy()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 546 void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);
3918 void MipsAsmParser::warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc) { in warnIfRegIndexIsAT() argument
3919 if (RegIndex != 0 && AssemblerOptions.back()->getATRegIndex() == RegIndex) in warnIfRegIndexIsAT()
3920 Warning(Loc, "used $at (currently $" + Twine(RegIndex) + in warnIfRegIndexIsAT()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 713 void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);
5932 void MipsAsmParser::warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc) { in warnIfRegIndexIsAT() argument
5933 if (RegIndex != 0 && AssemblerOptions.back()->getATRegIndex() == RegIndex) in warnIfRegIndexIsAT()
5934 Warning(Loc, "used $at (currently $" + Twine(RegIndex) + in warnIfRegIndexIsAT()
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