| /external/llvm/lib/Target/Lanai/InstPrinter/ |
| D | LanaiInstPrinter.cpp | 211 const MCOperand &RegOp) { in printMemoryBaseRegister() argument
212 assert(RegOp.isReg() && "Register operand expected"); in printMemoryBaseRegister()
216 OS << "%" << LanaiInstPrinter::getRegisterName(RegOp.getReg()); in printMemoryBaseRegister()
237 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand() local
246 printMemoryBaseRegister(OS, AluCode, RegOp); in printMemRiOperand()
252 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRrOperand() local
256 assert(OffsetOp.isReg() && RegOp.isReg() && "Registers expected."); in printMemRrOperand()
262 OS << "%" << getRegisterName(RegOp.getReg()); in printMemRrOperand()
273 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemSplsOperand() local
282 printMemoryBaseRegister(OS, AluCode, RegOp); in printMemSplsOperand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiInstPrinter.cpp | 214 const MCOperand &RegOp) { in printMemoryBaseRegister() argument
215 assert(RegOp.isReg() && "Register operand expected"); in printMemoryBaseRegister()
219 OS << "%" << LanaiInstPrinter::getRegisterName(RegOp.getReg()); in printMemoryBaseRegister()
240 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand() local
249 printMemoryBaseRegister(OS, AluCode, RegOp); in printMemRiOperand()
255 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRrOperand() local
259 assert(OffsetOp.isReg() && RegOp.isReg() && "Registers expected."); in printMemRrOperand()
265 OS << "%" << getRegisterName(RegOp.getReg()); in printMemRrOperand()
276 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemSplsOperand() local
285 printMemoryBaseRegister(OS, AluCode, RegOp); in printMemSplsOperand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 496 inline unsigned getRegState(const MachineOperand &RegOp) { in getRegState() argument
497 assert(RegOp.isReg() && "Not a register operand"); in getRegState()
498 return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) | in getRegState()
499 getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) | in getRegState()
500 getUndefRegState(RegOp.isUndef()) | in getRegState()
501 getInternalReadRegState(RegOp.isInternalRead()) | in getRegState()
502 getDebugRegState(RegOp.isDebug()) | in getRegState()
503 getRenamableRegState(Register::isPhysicalRegister(RegOp.getReg()) && in getRegState()
504 RegOp.isRenamable()); in getRegState()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 395 inline unsigned getRegState(const MachineOperand &RegOp) { in getRegState() argument
396 assert(RegOp.isReg() && "Not a register operand"); in getRegState()
397 return getDefRegState(RegOp.isDef()) | in getRegState()
398 getImplRegState(RegOp.isImplicit()) | in getRegState()
399 getKillRegState(RegOp.isKill()) | in getRegState()
400 getDeadRegState(RegOp.isDead()) | in getRegState()
401 getUndefRegState(RegOp.isUndef()) | in getRegState()
402 getInternalReadRegState(RegOp.isInternalRead()) | in getRegState()
403 getDebugRegState(RegOp.isDebug()); in getRegState()
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| /external/llvm/lib/Target/BPF/InstPrinter/ |
| D | BPFInstPrinter.cpp | 68 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemOperand() local
77 assert(RegOp.isReg() && "Register operand not a register"); in printMemOperand()
78 O << '(' << getRegisterName(RegOp.getReg()) << ')'; in printMemOperand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/MCTargetDesc/ |
| D | BPFInstPrinter.cpp | 67 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemOperand() local
71 assert(RegOp.isReg() && "Register operand not a register"); in printMemOperand()
72 O << getRegisterName(RegOp.getReg()); in printMemOperand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrFoldTables.h | 86 const X86MemoryFoldTableEntry *lookupTwoAddrFoldTable(unsigned RegOp);
90 const X86MemoryFoldTableEntry *lookupFoldTable(unsigned RegOp, unsigned OpNum);
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRAsmPrinter.cpp | 96 const MachineOperand &RegOp = MI->getOperand(OpNum); in PrintAsmOperand() local
98 assert(RegOp.isReg() && "Operand must be a register when you're" in PrintAsmOperand()
100 Register Reg = RegOp.getReg(); in PrintAsmOperand()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAsmPrinter.cpp | 132 unsigned RegOp = OpNo + 1; in PrintAsmOperand() local
133 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
135 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiAsmPrinter.cpp | 130 unsigned RegOp = OpNo + 1; in PrintAsmOperand() local
131 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
133 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/MCTargetDesc/ |
| D | AVRMCCodeEmitter.cpp | 137 auto RegOp = MI.getOperand(OpNo); in encodeMemri() local
140 assert(RegOp.isReg() && "Expected register operand"); in encodeMemri()
144 switch (RegOp.getReg()) { in encodeMemri()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 498 unsigned RegOp = OpNum; in PrintAsmOperand() local
504 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; in PrintAsmOperand()
507 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; in PrintAsmOperand()
510 RegOp = OpNum + 1; in PrintAsmOperand()
512 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
514 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 1388 const MachineOperand *RegOp = nullptr; in isOMod() local
1394 RegOp = Src1; in isOMod()
1397 RegOp = Src0; in isOMod()
1409 return std::make_pair(RegOp, OMod); in isOMod()
1439 const MachineOperand *RegOp; in tryFoldOMod() local
1441 std::tie(RegOp, OMod) = isOMod(MI); in tryFoldOMod()
1442 if (OMod == SIOutMods::NONE || !RegOp->isReg() || in tryFoldOMod()
1443 RegOp->getSubReg() != AMDGPU::NoSubRegister || in tryFoldOMod()
1444 !hasOneNonDBGUseInst(*MRI, RegOp->getReg())) in tryFoldOMod()
1447 MachineInstr *Def = MRI->getVRegDef(RegOp->getReg()); in tryFoldOMod()
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| D | SIInstrInfo.cpp | 875 MachineOperand RegOp = Cond[1]; in insertVectorSelect() local
876 RegOp.setImplicit(false); in insertVectorSelect()
879 .add(RegOp); in insertVectorSelect()
889 MachineOperand RegOp = Cond[1]; in insertVectorSelect() local
890 RegOp.setImplicit(false); in insertVectorSelect()
893 .add(RegOp); in insertVectorSelect()
1652 MachineOperand &RegOp, in swapRegAndNonRegOperand() argument
1654 Register Reg = RegOp.getReg(); in swapRegAndNonRegOperand()
1655 unsigned SubReg = RegOp.getSubReg(); in swapRegAndNonRegOperand()
1656 bool IsKill = RegOp.isKill(); in swapRegAndNonRegOperand()
[all …]
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| D | AMDGPUMachineCFGStructurizer.cpp | 1882 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true); in createIfBlock() local
1883 ArrayRef<MachineOperand> Cond(RegOp); in createIfBlock()
2341 MachineOperand RegOp = in createIfRegion() local
2343 ArrayRef<MachineOperand> Cond(RegOp); in createIfRegion()
2400 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true); in createIfRegion() local
2401 ArrayRef<MachineOperand> Cond(RegOp); in createIfRegion()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 586 unsigned RegOp = OpNum; in PrintAsmOperand() local
592 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; in PrintAsmOperand()
595 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; in PrintAsmOperand()
598 RegOp = OpNum + 1; in PrintAsmOperand()
600 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
602 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfCompileUnit.cpp | 511 const MachineOperand RegOp = DVInsn->getOperand(0); in constructVariableDIEImpl() local
514 MachineLocation Location(RegOp.getReg(), in constructVariableDIEImpl()
517 } else if (RegOp.getReg()) in constructVariableDIEImpl()
518 addVariableAddress(DV, *VariableDie, MachineLocation(RegOp.getReg())); in constructVariableDIEImpl()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/AsmParser/ |
| D | BPFAsmParser.cpp | 87 struct RegOp { struct
98 RegOp Reg;
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86Operand.h | 44 struct RegOp { struct
64 struct RegOp Reg;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86Operand.h | 46 struct RegOp { struct
75 struct RegOp Reg;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 1606 unsigned RegOp = CurOp++; in encodeInstruction() local
1613 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(RegOp)), in encodeInstruction()
1619 unsigned RegOp = CurOp++; in encodeInstruction() local
1623 emitRegModRMByte(MI.getOperand(RegOp), 0, CurByte, OS); in encodeInstruction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachinePipeliner.cpp | 358 MachineOperand &RegOp = PI.getOperand(i); in preprocessPhiNodes() local
359 if (RegOp.getSubReg() == 0) in preprocessPhiNodes()
369 .addReg(RegOp.getReg(), getRegState(RegOp), in preprocessPhiNodes()
370 RegOp.getSubReg()); in preprocessPhiNodes()
372 RegOp.setReg(NewReg); in preprocessPhiNodes()
373 RegOp.setSubReg(0); in preprocessPhiNodes()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 165 uint16_t RegOp, uint16_t MemOp, uint16_t Flags);
|
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 86 struct RegOp { struct in __anon1e4944a50111::SystemZOperand
113 RegOp Reg;
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| /external/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 105 struct RegOp { struct
122 struct RegOp Reg;
|