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Searched refs:RegionBegin (Results 1 – 17 of 17) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DGCNSchedStrategy.cpp327 Regions.push_back(std::make_pair(RegionBegin, RegionEnd)); in schedule()
350 Regions[RegionIdx] = std::make_pair(RegionBegin, RegionEnd); in schedule()
406 RegionEnd = RegionBegin; in schedule()
437 RegionBegin = Unsched.front()->getIterator(); in schedule()
438 Regions[RegionIdx] = std::make_pair(RegionBegin, RegionEnd); in schedule()
562 RegionBegin = Region.first; in finalizeSchedule()
565 if (RegionBegin->getParent() != MBB) { in finalizeSchedule()
567 MBB = RegionBegin->getParent(); in finalizeSchedule()
DGCNIterativeScheduler.cpp202 assert(Sch.RegionBegin == Rgn.Begin && Sch.RegionEnd == Rgn.End); in schedule()
210 Rgn.Begin = Sch.RegionBegin; in schedule()
215 assert(Sch.RegionBegin == Rgn.Begin && Sch.RegionEnd == Rgn.End); in restoreOrder()
314 LLVM_DEBUG(printLivenessInfo(dbgs(), RegionBegin, RegionEnd, LIS); in schedule()
315 if (!Regions.empty() && Regions.back()->Begin == RegionBegin) { in schedule()
374 assert(RegionBegin == R.Begin && RegionEnd == R.End); in scheduleRegion()
404 RegionBegin = getMachineInstr(Schedule.front()); in scheduleRegion()
415 R.Begin = RegionBegin; in scheduleRegion()
DSIMachineScheduler.h451 RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false); in initRPTracker()
DSIMachineScheduler.cpp2020 assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker"); in schedule()
/external/llvm/include/llvm/CodeGen/
DScheduleDAGInstrs.h129 MachineBasicBlock::iterator RegionBegin; variable
253 MachineBasicBlock::iterator begin() const { return RegionBegin; } in begin()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DScheduleDAGInstrs.h148 MachineBasicBlock::iterator RegionBegin; variable
272 MachineBasicBlock::iterator begin() const { return RegionBegin; } in begin()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DPostRASchedulerList.cpp397 AntiDepBreak->BreakAntiDependencies(SUnits, RegionBegin, RegionEnd, in schedule()
673 RegionBegin = RegionEnd; in EmitSchedule()
690 RegionBegin = std::prev(RegionEnd); in EmitSchedule()
DMachineScheduler.cpp457 MachineBasicBlock::iterator RegionBegin; member
463 RegionBegin(B), RegionEnd(E), NumRegionInstrs(N) {} in SchedRegion()
549 MachineBasicBlock::iterator I = R->RegionBegin; in scheduleRegions()
719 if (&*RegionBegin == MI) in moveInstruction()
720 ++RegionBegin; in moveInstruction()
730 if (RegionBegin == InsertPos) in moveInstruction()
731 RegionBegin = MI; in moveInstruction()
873 CurrentTop = nextIfDebug(RegionBegin, RegionEnd); in initQueues()
892 BB->splice(RegionBegin, BB, FirstDbgValue); in placeDebugValues()
893 RegionBegin = FirstDbgValue; in placeDebugValues()
[all …]
DScheduleDAGInstrs.cpp191 RegionBegin = begin; in enterRegion()
570 for (MachineInstr &MI : make_range(RegionBegin, RegionEnd)) { in initSUnits()
798 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin; in buildSchedGraph()
/external/llvm/lib/CodeGen/
DPostRASchedulerList.cpp397 AntiDepBreak->BreakAntiDependencies(SUnits, RegionBegin, RegionEnd, in schedule()
675 RegionBegin = RegionEnd; in EmitSchedule()
692 RegionBegin = std::prev(RegionEnd); in EmitSchedule()
DMachineScheduler.cpp647 if (&*RegionBegin == MI) in moveInstruction()
648 ++RegionBegin; in moveInstruction()
658 if (RegionBegin == InsertPos) in moveInstruction()
659 RegionBegin = MI; in moveInstruction()
807 CurrentTop = nextIfDebug(RegionBegin, RegionEnd); in initQueues()
826 BB->splice(RegionBegin, BB, FirstDbgValue); in placeDebugValues()
827 RegionBegin = FirstDbgValue; in placeDebugValues()
835 if (&*RegionBegin == DbgValue) in placeDebugValues()
836 ++RegionBegin; in placeDebugValues()
892 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, in initRegPressure()
[all …]
DScheduleDAGInstrs.cpp230 RegionBegin = begin; in enterRegion()
648 for (MachineInstr &MI : llvm::make_range(RegionBegin, RegionEnd)) { in initSUnits()
913 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin; in buildSchedGraph()
/external/scudo/standalone/
Dprimary64.h406 B.RegionBegin = RegionInfoArray[ClassId].RegionBeg; in findNearestBlock()
407 B.RegionEnd = B.RegionBegin + RegionInfoArray[ClassId].AllocatedUser; in findNearestBlock()
410 B.RegionBegin + uptr(sptr(Ptr - B.RegionBegin) / sptr(B.BlockSize) * in findNearestBlock()
412 while (B.BlockBegin < B.RegionBegin) in findNearestBlock()
Dcommon.h204 uptr RegionBegin; member
Dcombined.h1388 if (BlockAddr < Info.RegionBegin || BlockAddr >= Info.RegionEnd) in getInlineErrorInfo()
/external/llvm/lib/Target/AMDGPU/
DSIMachineScheduler.h444 RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false); in initRPTracker()
DSIMachineScheduler.cpp1880 assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker"); in schedule()