Searched refs:RegisterMask (Results 1 – 14 of 14) sorted by relevance
| /external/llvm/tools/llvm-readobj/ |
| D | ARMWinEHPrinter.cpp | 148 void Decoder::printRegisters(const std::pair<uint16_t, uint32_t> &RegisterMask) { in printRegisters() argument
154 const uint16_t GPRMask = std::get<0>(RegisterMask); in printRegisters()
155 const uint16_t VFPMask = std::get<1>(RegisterMask); in printRegisters()
241 uint16_t RegisterMask = (Link << (Prologue ? 14 : 15)) in opcode_10Lxxxxx() local
244 assert((~RegisterMask & (1 << 13)) && "sp must not be set"); in opcode_10Lxxxxx()
245 assert((~RegisterMask & (1 << (Prologue ? 15 : 14))) && "pc must not be set"); in opcode_10Lxxxxx()
250 printRegisters(std::make_pair(RegisterMask, 0)); in opcode_10Lxxxxx()
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| D | ARMWinEHPrinter.h | 81 void printRegisters(const std::pair<uint16_t, uint32_t> &RegisterMask);
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/Stages/ |
| D | DispatchStage.cpp | 51 const unsigned RegisterMask = PRF.isAvailable(RegDefs); in checkPRF() local
53 if (RegisterMask) { in checkPRF()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, enumerator
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| D | SelectionDAGNodes.h | 1643 : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
1650 return N->getOpcode() == ISD::RegisterMask;
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 61 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, enumerator
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| D | SelectionDAGNodes.h | 2063 : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
2070 return N->getOpcode() == ISD::RegisterMask;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 91 case ISD::RegisterMask: return "RegisterMask"; in getOperationName()
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| D | SelectionDAGISel.cpp | 2739 case ISD::RegisterMask: in SelectCodeCommon()
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| D | SelectionDAG.cpp | 415 case ISD::RegisterMask: in AddNodeIDCustom()
1694 AddNodeIDNode(ID, ISD::RegisterMask, getVTList(MVT::Untyped), None); in getRegisterMask()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 113 case ISD::RegisterMask: return "RegisterMask"; in getOperationName()
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| D | SelectionDAGISel.cpp | 2783 case ISD::RegisterMask: in SelectCodeCommon()
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| D | SelectionDAG.cpp | 521 case ISD::RegisterMask: in AddNodeIDCustom()
1807 AddNodeIDNode(ID, ISD::RegisterMask, getVTList(MVT::Untyped), None); in getRegisterMask()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 3642 SDValue RegisterMask = DAG.getRegisterMask(Mask); in LowerINTRINSIC_VOID() local
3648 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}), in LowerINTRINSIC_VOID()
3652 {ReturnAddress, Callee, RegisterMask, Chain}), in LowerINTRINSIC_VOID()
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