| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCInstrFormats.td | 178 bits<25> S25; // 2-byte aligned 25-bit byte-offset.
179 let Inst{26-18} = S25{10-2};
180 let Inst{15-6} = S25{20-11};
182 let Inst{3-0} = S25{24-21};
190 // Branch targets are 2-byte aligned, so S25[0] is implied 0.
192 // |S25[10-1] | 1|S25[20-11] |N|0|S25[24-21]|
195 let Inst{17} = S25{1};
198 // BL targets (functions) are 4-byte aligned, so S25[1-0] = 0b00
200 // |S25[10-2] | 1| 0|S25[20-11] |N|0|S25[24-21]|
208 // |S25[10-2] | 0| 0|S25[20-11] |N|0|cc |
|
| D | ARCInstrInfo.td | 325 def BR : F32_BR0_UCOND_FAR<(outs), (ins btargetS25:$S25),
326 "b\t$S25", [(br bb:$S25)]>;
375 def BL : F32_BR1_BL_UCOND_FAR<(outs), (ins calltargetS25:$S25),
376 "bl\t$S25", [(ARCBranchLink tglobaladdr:$S25)]>;
|
| /external/clang/test/PCH/ |
| D | cxx-key-functions.cpp | 33 struct S25 { virtual void f(); }; struct
84 S20, S21, S22, S23, S24, S25, S26, S27, S28, S29,
|
| /external/clang/test/CodeGenCXX/ |
| D | microsoft-abi-static-initializers.cpp | 84 static S S25; in MultipleStatics() local
|
| /external/OpenCSD/decoder/tests/snapshots/trace_cov_a15/ |
| D | device1.ini | 305 S25=0x00100800 key
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 60 case AArch64::S25: in isOdd()
|
| D | AArch64RegisterInfo.td | 310 def S25 : AArch64Reg<25, "s25", [H25]>, DwarfRegAlias<B25>;
345 def D25 : AArch64Reg<25, "d25", [S25], ["v25", ""]>, DwarfRegAlias<B25>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 59 case AArch64::S25: in isOdd()
|
| D | AArch64SchedPredicates.td | 125 CheckRegOperand<0, S25>,
|
| D | AArch64RegisterInfo.td | 343 def S25 : AArch64Reg<25, "s25", [H25]>, DwarfRegAlias<B25>;
378 def D25 : AArch64Reg<25, "d25", [S25], ["v25", ""]>, DwarfRegAlias<B25>;
|
| /external/OpenCSD/decoder/tests/snapshots/tc2-ptm-rstk-t32/ |
| D | device1.ini | 305 S25=0x00100800 key
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 93 def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;
112 def D12 : ARMReg<12, "d12", [S24, S25]>, DwarfRegNum<[268]>;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenRegisterInfo.inc | 164 S25 = 144,
1506 …PPC::S11, PPC::S12, PPC::S30, PPC::S29, PPC::S28, PPC::S27, PPC::S26, PPC::S25, PPC::S24, PPC::S23…
1526 …PPC::S11, PPC::S12, PPC::S30, PPC::S29, PPC::S28, PPC::S27, PPC::S26, PPC::S25, PPC::S24, PPC::S23…
1880 { 1225U, PPC::S25 },
2023 { 1225U, PPC::S25 },
2168 { 1225U, PPC::S25 },
2311 { 1225U, PPC::S25 },
2460 { PPC::S25, 1225U },
2735 { PPC::S25, 1225U },
3013 { PPC::S25, 1225U },
[all …]
|
| /external/OpenCSD/decoder/tests/snapshots/a55-test-tpiu/ |
| D | device1.ini | 192 S25=0x00000000 key
|
| /external/OpenCSD/decoder/tests/snapshots/a57_single_step/ |
| D | device1.ini | 192 S25=0x00000000 key
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCTargetDesc.cpp | 156 {codeview::RegisterId::ARM64_S25, AArch64::S25}, in initLLVMToCVRegMapping()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 112 def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;
131 def D12 : ARMReg<12, "d12", [S24, S25]>, DwarfRegNum<[268]>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 305 S23, S24, S25, S26, S27, S28, S29, S30, S31
|
| D | PPCFrameLowering.cpp | 202 {PPC::S25, -56}, in getCalleeSavedSpillSlots()
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenRegisterInfo.inc | 130 S25 = 110,
1521 { ARM::S25 },
1567 …ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27…
1577 …ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27…
1587 …ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27…
5903 …ARM::S11, ARM::S13, ARM::S15, ARM::S17, ARM::S19, ARM::S21, ARM::S23, ARM::S25, ARM::S27, ARM::S29…
5904 …6, ARM::S30, ARM::S1, ARM::S5, ARM::S9, ARM::S13, ARM::S17, ARM::S21, ARM::S25, ARM::S29, ARM::S3,…
5921 …ARM::S11, ARM::S13, ARM::S15, ARM::S17, ARM::S19, ARM::S21, ARM::S23, ARM::S25, ARM::S27, ARM::S29…
5922 …6, ARM::S30, ARM::S1, ARM::S5, ARM::S9, ARM::S13, ARM::S17, ARM::S21, ARM::S25, ARM::S29, ARM::S3,…
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 311 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 360 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterInfo.inc | 198 S25 = 178,
2330 …h64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArc…
3959 { AArch64::S25, 89U },
4238 { AArch64::S25, 89U },
20422 …h64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArc…
20424 …h64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArc…
|
| D | AArch64GenSubtargetInfo.inc | 13966 || MI->getOperand(0).getReg() == AArch64::S25
14120 || MI->getOperand(0).getReg() == AArch64::S25
14274 || MI->getOperand(0).getReg() == AArch64::S25
19602 || MI->getOperand(0).getReg() == AArch64::S25
19756 || MI->getOperand(0).getReg() == AArch64::S25
19910 || MI->getOperand(0).getReg() == AArch64::S25
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 997 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
|