Searched refs:SEC_SRAM_BASE (Results 1 – 8 of 8) sorted by relevance
210 rc = fdt_add_mem_rsv(dtb, SEC_SRAM_BASE, SEC_SRAM_SIZE); in rpi3_dtb_add_mem_rsv()215 INFO("rpi3: Reserved 0x%llx - 0x%llx in DTB\n", SEC_SRAM_BASE, in rpi3_dtb_add_mem_rsv()216 SEC_SRAM_BASE + SEC_SRAM_SIZE); in rpi3_dtb_add_mem_rsv()
75 #define SEC_SRAM_BASE ULL(0x00200000) macro93 #define SEC_SRAM_BASE ULL(0x10000000) macro119 #define SHARED_RAM_BASE SEC_SRAM_BASE
86 #define SEC_SRAM_BASE 0x0e000000 macro105 #define SHARED_RAM_BASE SEC_SRAM_BASE
33 #define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */ macro
35 #define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */ macro
74 #define SEC_SRAM_BASE 0x20000000 macro91 #define SHARED_RAM_BASE SEC_SRAM_BASE
53 #define BL31_BASE SEC_SRAM_BASE
1366 - Explicitly map SEC_SRAM_BASE to 0x0