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Searched refs:SMLSLD (Results 1 – 23 of 23) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelLowering.h219 SMLSLD, // Signed multiply subtract long dual enumerator
DARMScheduleR52.td280 "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX",
DARMScheduleSwift.td308 "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX",
DARMScheduleA9.td2557 "SMLSLD", "SMLSLDX", "SMUAD", "SMUADX", "SMUSD", "SMUSDX")>;
DARMInstrInfo.td114 def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>;
4493 (SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
DARMISelLowering.cpp1666 case ARMISD::SMLSLD: return "ARMISD::SMLSLD"; in getTargetNodeName()
9394 Opc = ARMISD::SMLSLD; in ReplaceLongIntrinsic()
DARMInstrThumb2.td3073 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
/external/llvm/lib/Target/ARM/
DARMScheduleSwift.td292 "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX",
DARMScheduleA9.td2507 "SMLSLD", "SMLLDX", "SMUAD", "SMUADX", "SMUSD", "SMUSDX")>;
DARMInstrThumb2.td2849 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenAsmWriter.inc2435 3263638U, // SMLSLD
6659 33554432U, // SMLSLD
11441 case ARM::SMLSLD:
11547 case ARM::SMLSLD:
DARMGenMCCodeEmitter.inc1743 UINT64_C(121634896), // SMLSLD
15661 case ARM::SMLSLD:
18418 CEFBS_IsARM_HasV6, // SMLSLD = 1730
DARMGenInstrInfo.inc1745 SMLSLD = 1730,
7576 …CID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1730 = SMLSLD
DARMGenAsmMatcher.inc11141 …{ 1226 /* smlsld */, ARM::SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__Con…
DARMGenDisassemblerTables.inc1411 /* 6475 */ MCD::OPC_Decode, 194, 13, 19, // Opcode: SMLSLD
DARMGenDAGISel.inc48305 /*104874*/ /*SwitchOpcode*/ 50, TARGET_VAL(ARMISD::SMLSLD),// ->104927
48314 /*104891*/ OPC_MorphNodeTo2, TARGET_VAL(ARM::SMLSLD), 0,
48317 …// Dst: (SMLSLD:{ *:[i32] }:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:…
/external/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1683 # SMLSLD/SMLSLDX
Dthumb2.txt1868 # SMLSLD/SMLSLDX
/external/llvm/test/MC/ARM/
Dbasic-thumb2-instructions.s2385 @ SMLSLD/SMLSLDX
Dbasic-arm-instructions.s2475 @ SMLSLD/SMLSLDX
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc372 30462U, // SMLSLD
3176 17842176U, // SMLSLD
DARMGenInstrInfo.inc3563 …nmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #355 = SMLSLD
DARMGenDisassemblerTables.inc1360 /* 5480 */ MCD_OPC_Decode, 227, 2, 19, // Opcode: SMLSLD