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Searched refs:SOPP (Results 1 – 19 of 19) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSOPInstructions.td935 // SOPP Instructions
950 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
957 let SOPP = 1;
964 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
984 let SOPP = 1;
992 def "" : SOPP <op, ins, asm, pattern>;
998 def S_ENDPGM : SOPP <0x00000001, (ins EndpgmImm:$simm16), "s_endpgm$simm16"> {
1003 def S_ENDPGM_SAVED : SOPP <0x0000001B, (ins), "s_endpgm_saved"> {
1013 SOPP<0x01e, (ins), "s_endpgm_ordered_ps_done">;
1020 SOPP<0x01f, (ins), "s_code_end">;
[all …]
DSIInstrFormats.td25 field bit SOPP = 0;
138 let TSFlags{6} = SOPP;
DSIDefines.h29 SOPP = 1 << 6, enumerator
DSIInstrInfo.h390 return MI.getDesc().TSFlags & SIInstrFlags::SOPP; in isSOPP()
394 return get(Opcode).TSFlags & SIInstrFlags::SOPP; in isSOPP()
DSIInstrInfo.td2530 // Maps a SOPP to a SOPP with S_NOP
/external/mesa3d/src/amd/compiler/
Daco_opcodes.py38 SOPP = 4 variable in Format
65 elif self == Format.SOPP:
497 SOPP = { variable
539 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPP:
540 opcode(name, gfx7, gfx9, gfx10, Format.SOPP)
Daco_statistics.cpp49 … if (instr->format == Format::SOPP && static_cast<SOPP_instruction*>(instr.get())->block != -1) in collect_preasm_stats()
Daco_insert_NOPs.cpp425 …SOPP_instruction> nop{create_instruction<SOPP_instruction>(aco_opcode::s_nop, Format::SOPP, 0, 0)}; in handle_instruction_gfx6()
623 …on> depctr{create_instruction<SOPP_instruction>(aco_opcode::s_waitcnt_depctr, Format::SOPP, 0, 0)}; in handle_instruction_gfx10()
662 …on> depctr{create_instruction<SOPP_instruction>(aco_opcode::s_waitcnt_depctr, Format::SOPP, 0, 0)}; in handle_instruction_gfx10()
695 if (instr->format != Format::SOPP) { in handle_instruction_gfx10()
Daco_opt_value_numbering.cpp99 case Format::SOPP: in operator ()()
290 case Format::SOPP: in operator ()()
Daco_insert_waitcnt.cpp842 case Format::SOPP: { in gen()
863 …ruction* waitcnt = create_instruction<SOPP_instruction>(aco_opcode::s_waitcnt, Format::SOPP, 0, 0); in emit_waitcnt()
DREADME-ISA.md178 Any non-SOPP SALU instruction (except `s_setvskip`, `s_version`, and any non-lgkmcnt `s_waitcnt`).
Daco_ir.h75 SOPP = 4, enumerator
932 format == Format::SOPP; in isSALU()
Daco_print_ir.cpp269 case Format::SOPP: { in print_instr_format_specific()
Daco_assembler.cpp159 case Format::SOPP: { in emit_instruction()
/external/llvm/docs/
DAMDGPUUsage.rst75 SOPP Instructions
78 Unless otherwise mentioned, all SOPP instructions that have one or more
/external/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td29 field bits<1> SOPP = 0;
65 let TSFlags{9} = SOPP;
331 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
338 let SOPP = 1;
DSIInstructions.td421 // SOPP Instructions
424 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
428 def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm",
437 def S_BRANCH : SOPP <
444 def S_CBRANCH_SCC0 : SOPP <
448 def S_CBRANCH_SCC1 : SOPP <
456 def S_CBRANCH_VCCZ : SOPP <
460 def S_CBRANCH_VCCNZ : SOPP <
467 def S_CBRANCH_EXECZ : SOPP <
471 def S_CBRANCH_EXECNZ : SOPP <
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DSIDefines.h26 SOPP = 1 << 9, enumerator
DSIInstrInfo.h240 return MI.getDesc().TSFlags & SIInstrFlags::SOPP; in isSOPP()
244 return get(Opcode).TSFlags & SIInstrFlags::SOPP; in isSOPP()