SPR (reference) in projects: external - OpenGrok search results

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Searched refs:SPR (Results 1 – 25 of 41) sorted by relevance

/external/llvm/lib/Target/ARM/
D	ARMInstrVFP.td	105 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), 107 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]> { 113 def VLDRH : AHI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5fp16:$addr), 124 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), 126 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]> { 132 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5fp16:$addr), 343 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 345 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> { 353 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 365 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), [all …]
D	ARMRegisterInfo.td	`272 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> { 273 let AltOrders = [(add (decimate SPR, 2), SPR), 274 (add (decimate SPR, 4), 275 (decimate SPR, 2), 276 (decimate (rotl SPR, 1), 4), 277 (decimate (rotl SPR, 1), 2))]; 283 // Subset of SPR which can be used as a source of NEON scalars for 16-bit 303 // 32-bit SPR subregs). 320 // Subset of QPR that have 32-bit SPR subregs.`
D	ARMInstrNEON.td	4219 def : Pat<(v2f32 (fmul DPR:$Rn, (NEONvdup (f32 SPR:$Rm)))), 4221 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0), 4223 def : Pat<(v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm)))), 4225 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0), 5935 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)), 5937 SPR:$src2, (SSubReg_f32_reg imm:$src3))>; 5938 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)), 5940 SPR:$src2, (SSubReg_f32_reg imm:$src3))>; 5947 def : Pat<(v2f32 (scalar_to_vector SPR:$src)), 5948 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>; [all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
D	ARMInstrVFP.td	149 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), 151 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]>, 171 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), 173 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]>, 377 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 379 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>, 402 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 404 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>, 427 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 429 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>, [all …]
D	ARMRegisterInfo.td	`370 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> { 371 let AltOrders = [(add (decimate SPR, 2), SPR), 372 (add (decimate SPR, 4), 373 (decimate SPR, 2), 374 (decimate (rotl SPR, 1), 4), 375 (decimate (rotl SPR, 1), 2))]; 383 let AltOrders = [(add (decimate HPR, 2), SPR), 394 // Subset of SPR which can be used as a source of NEON scalars for 16-bit 419 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> { 424 // 32-bit SPR subregs). [all …]`
D	ARMRegisterBanks.td	`13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;`
D	ARMInstrNEON.td	4364 def : Pat<(v2f32 (fmul DPR:$Rn, (ARMvdup (f32 SPR:$Rm)))), 4366 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0), 4372 def : Pat<(v4f32 (fmul QPR:$Rn, (ARMvdup (f32 SPR:$Rm)))), 4374 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0), 5215 (ins SPR:$Vn, SPR_8:$Vm, VectorIndex32:$idx), 5237 def VFMALD : N3VCP8F16Q0<"vfmal", DPR, SPR, SPR, 0b00, 0b10, 1>; 5238 def VFMSLD : N3VCP8F16Q0<"vfmsl", DPR, SPR, SPR, 0b01, 0b10, 1>; 6438 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)), 6440 SPR:$src2, (SSubReg_f32_reg imm:$src3))>; 6441 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)), [all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
D	PPCRegisterInfo.td	47 // SPR - One of the 32-bit special-purpose registers 48 class SPR<bits<10> num, string n> : PPCReg<n> { 218 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 220 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 223 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 224 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 227 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; 233 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>; 235 def XER: SPR<1, "xer">, DwarfRegNum<[76]>; 238 // (which really is SPR register 1); this is the only bit interesting to a [all …]
D	PPCInstrFormats.td	`1560 bits<10> SPR; 1563 let Inst{11} = SPR{4}; 1564 let Inst{12} = SPR{3}; 1565 let Inst{13} = SPR{2}; 1566 let Inst{14} = SPR{1}; 1567 let Inst{15} = SPR{0}; 1568 let Inst{16} = SPR{9}; 1569 let Inst{17} = SPR{8}; 1570 let Inst{18} = SPR{7}; 1571 let Inst{19} = SPR{6}; [all …]`
D	PPCInstr64Bit.td	`373 def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 374 "mfspr $RT, $SPR", IIC_SprMFSPR>; 375 def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 376 "mtspr $SPR, $RT", IIC_SprMTSPR>; 380 // 64-bit SPR manipulation instrs.`
D	PPCInstrInfo.td	2666 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR), 2667 "mfspr $RT, $SPR", IIC_SprMFSPR>; 2668 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), 2669 "mtspr $SPR, $RT", IIC_SprMTSPR>; 2671 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), 2672 "mftb $RT, $SPR", IIC_SprMFTB>; 2674 def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR), 2675 "mfpmr $RT, $SPR", IIC_SprMFPMR>; 2677 def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT), 2678 "mtpmr $SPR, $RT", IIC_SprMTPMR>; [all …]
/external/llvm/lib/Target/PowerPC/
D	PPCRegisterInfo.td	`42 // SPR - One of the 32-bit special-purpose registers 43 class SPR<bits<10> num, string n> : PPCReg<n> { 205 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 207 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 210 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 211 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 214 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; 217 // (which really is SPR register 1); this is the only bit interesting to a 219 def CARRY: SPR<1, "ca">, DwarfRegNum<[76]>;`
D	PPCInstrFormats.td	`1345 bits<10> SPR; 1348 let Inst{11} = SPR{4}; 1349 let Inst{12} = SPR{3}; 1350 let Inst{13} = SPR{2}; 1351 let Inst{14} = SPR{1}; 1352 let Inst{15} = SPR{0}; 1353 let Inst{16} = SPR{9}; 1354 let Inst{17} = SPR{8}; 1355 let Inst{18} = SPR{7}; 1356 let Inst{19} = SPR{6}; [all …]`
D	PPCInstr64Bit.td	`356 def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 357 "mfspr $RT, $SPR", IIC_SprMFSPR>; 358 def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 359 "mtspr $SPR, $RT", IIC_SprMTSPR>; 363 // 64-bit SPR manipulation instrs.`
D	PPCInstrInfo.td	2295 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR), 2296 "mfspr $RT, $SPR", IIC_SprMFSPR>; 2297 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), 2298 "mtspr $SPR, $RT", IIC_SprMTSPR>; 2300 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), 2301 "mftb $RT, $SPR", IIC_SprMFTB>; 2338 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 3678 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR), 3679 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; 3680 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR), [all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
D	ARMGenDAGISel.inc	10821 …:$p1, (ARMvcmp:{ :[v4i1] } MQPR:{ :[v4f32] }:$v1, (ARMvdup:{ :[v4f32] } SPR:{ :[f32] }:$v2), 0… 10822 …CMPf32r:{ :[v4i1] } MQPR:{ :[v4f32] }:$v1, (COPY_TO_REGCLASS:{ :[i32] } SPR:{ :[f32] }:$v2, rG… 10836 …:$p1, (ARMvcmp:{ :[v4i1] } MQPR:{ :[v4f32] }:$v1, (ARMvdup:{ :[v4f32] } SPR:{ :[f32] }:$v2), 1… 10837 …CMPf32r:{ :[v4i1] } MQPR:{ :[v4f32] }:$v1, (COPY_TO_REGCLASS:{ :[i32] } SPR:{ :[f32] }:$v2, rG… 10851 …:$p1, (ARMvcmp:{ :[v4i1] } MQPR:{ :[v4f32] }:$v1, (ARMvdup:{ :[v4f32] } SPR:{ :[f32] }:$v2), 1… 10852 …CMPf32r:{ :[v4i1] } MQPR:{ :[v4f32] }:$v1, (COPY_TO_REGCLASS:{ :[i32] } SPR:{ :[f32] }:$v2, rG… 10866 …:$p1, (ARMvcmp:{ :[v4i1] } MQPR:{ :[v4f32] }:$v1, (ARMvdup:{ :[v4f32] } SPR:{ :[f32] }:$v2), 1… 10867 …CMPf32r:{ :[v4i1] } MQPR:{ :[v4f32] }:$v1, (COPY_TO_REGCLASS:{ :[i32] } SPR:{ :[f32] }:$v2, rG… 10881 …:$p1, (ARMvcmp:{ :[v4i1] } MQPR:{ :[v4f32] }:$v1, (ARMvdup:{ :[v4f32] } SPR:{ :[f32] }:$v2), 1… 10882 …CMPf32r:{ :[v4i1] } MQPR:{ :[v4f32] }:$v1, (COPY_TO_REGCLASS:{ :[i32] } SPR:{ :[f32] }:$v2, rG… [all …]
D	ARMGenInstrInfo.inc	14854 SPR = 325, 19528 OpTypes::SPR, OpTypes::SPR, OpTypes::SPR, OpTypes::i32imm, OpTypes::i32imm, 19769 OpTypes::SPR, OpTypes::vfp_f32imm, OpTypes::i32imm, OpTypes::i32imm, 21023 OpTypes::SPR, OpTypes::SPR, OpTypes::i32imm, OpTypes::i32imm, 21053 OpTypes::SPR, OpTypes::SPR, OpTypes::SPR, OpTypes::i32imm, OpTypes::i32imm, 21205 OpTypes::SPR, OpTypes::SPR, OpTypes::i32imm, OpTypes::i32imm, 21208 OpTypes::SPR, OpTypes::i32imm, OpTypes::i32imm, 21210 OpTypes::SPR, OpTypes::SPR, OpTypes::i32imm, OpTypes::i32imm, 21213 OpTypes::SPR, OpTypes::i32imm, OpTypes::i32imm, 21224 OpTypes::SPR, OpTypes::DPR, [all …]
D	ARMGenGlobalISel.inc	8034 … // (bitconvert:{ :[i32] } SPR:{ :[f32] }:$Sn) => (VMOVRS:{ :[i32] } SPR:{ :[f32] }:$Sn) 11748 // (ftrunc:{ :[f32] } SPR:{ :[f32] }:$Sm) => (VRINTZS:{ :[f32] } SPR:{ :[f32] }:$Sm) 11850 // (fround:{ :[f32] } SPR:{ :[f32] }:$Sm) => (VRINTAS:{ :[f32] } SPR:{ :[f32] }:$Sm) 11980 …(intrinsic_wo_chain:{ :[f32] } 1747:{ :[iPTR] }, SPR:{ :[f32] }:$Sm) => (VRINTNS:{ :[f32] } … 12030 …(intrinsic_wo_chain:{ :[f32] } 1862:{ :[iPTR] }, SPR:{ :[f32] }:$Sm) => (VTOSIRS:{ :[f32] } … 12066 …(intrinsic_wo_chain:{ :[f32] } 1863:{ :[iPTR] }, SPR:{ :[f32] }:$Sm) => (VTOUIRS:{ :[f32] } … 24213 …8] } 0:{ :[i64] }, (COPY_TO_REGCLASS:{ :[f32] } i32:{ :[i32] }:$hash_e, SPR:{ :[i32] }), ssub_… 24226 GIR_ConstrainOperandRC, /InsnID/1, /Op/2, /RC SPR/2, 24245 …8] } 0:{ :[i64] }, (COPY_TO_REGCLASS:{ :[f32] } i32:{ :[i32] }:$hash_e, SPR:{ :[i32] }), ssub_… 24258 GIR_ConstrainOperandRC, /InsnID/1, /Op/2, /RC SPR/2, [all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
D	LazyValueInfo.cpp	`895 SelectPatternResult SPR = matchSelectPattern(SI, LHS, RHS); in solveBlockValueSelect() local 898 if (SelectPatternResult::isMinOrMax(SPR.Flavor) && in solveBlockValueSelect() 901 switch (SPR.Flavor) { in solveBlockValueSelect() 918 if (SPR.Flavor == SPF_ABS) { in solveBlockValueSelect() 929 if (SPR.Flavor == SPF_NABS) { in solveBlockValueSelect()`
D	ValueTracking.cpp	`4853 SelectPatternResult SPR = matchClamp(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal); in matchMinMax() local 4854 if (SPR.Flavor != SelectPatternFlavor::SPF_UNKNOWN) in matchMinMax() 4855 return SPR; in matchMinMax() 4857 SPR = matchMinMaxOfMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal, Depth); in matchMinMax() 4858 if (SPR.Flavor != SelectPatternFlavor::SPF_UNKNOWN) in matchMinMax() 4859 return SPR; in matchMinMax()`
/external/llvm/lib/Transforms/InstCombine/
D	InstCombineSelect.cpp	`1105 SelectPatternResult SPR = matchSelectPattern(&SI, LHS, RHS, &CastOp); in visitSelectInst() local 1106 auto SPF = SPR.Flavor; in visitSelectInst() 1112 CmpInst::Predicate Pred = getCmpPredicateForMinMax(SPF, SPR.Ordered); in visitSelectInst()`
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/
D	InstCombineSelect.cpp	1006 SelectPatternResult SPR = matchSelectPattern(&Sel, LHS, RHS); in canonicalizeMinMaxWithConstant() local 1007 if (!SelectPatternResult::isMinOrMax(SPR.Flavor)) in canonicalizeMinMaxWithConstant() 1011 ICmpInst::Predicate CanonicalPred = getMinMaxPred(SPR.Flavor); in canonicalizeMinMaxWithConstant() 2541 SelectPatternResult SPR = matchSelectPattern(&SI, LHS, RHS, &CastOp); in visitSelectInst() local 2542 auto SPF = SPR.Flavor; in visitSelectInst() 2569 CmpInst::Predicate MinMaxPred = getMinMaxPred(SPF, SPR.Ordered); in visitSelectInst()
/external/capstone/arch/ARM/
D	ARMGenAsmWriter.inc	`8850 // (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p) 9499 // (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p) 9917 // (VCMPZS SPR:$val, pred:$p) 9935 // (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p) 9972 // (VMOVS SPR:$Sd, SPR:$Sm, pred:$p) 10034 // (VRINTAS SPR:$Sd, SPR:$Sm) 10078 // (VRINTMS SPR:$Sd, SPR:$Sm) 10122 // (VRINTNS SPR:$Sd, SPR:$Sm) 10166 // (VRINTPS SPR:$Sd, SPR:$Sm) 10188 // (VRINTRS SPR:$Sd, SPR:$Sm, pred:$p) [all …]`
D	ARMGenRegisterInfo.inc	`1179 // SPR Register Class... 1180 static MCPhysReg SPR[] = { 1184 // SPR Bit set. 2180 { SPR, SPRBits, 2228, 32, sizeof(SPRBits), ARM_SPRRegClassID, 4, 4, 1, 1 },`
/external/llvm/lib/Analysis/
D	LazyValueInfo.cpp	`914 SelectPatternResult SPR = matchSelectPattern(SI, LHS, RHS); in solveBlockValueSelect() local 917 if (SelectPatternResult::isMinOrMax(SPR.Flavor) && in solveBlockValueSelect() 919 switch (SPR.Flavor) { in solveBlockValueSelect()`

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