| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 44 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift() argument
46 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) in printRegImmShift()
50 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); in printRegImmShift()
51 O << getShiftOpcStr(ShOpc); in printRegImmShift()
53 if (ShOpc != ARM_AM::rrx) { in printRegImmShift()
352 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand() local
353 O << ", " << ARM_AM::getShiftOpcStr(ShOpc); in printSORegRegOperand()
354 if (ShOpc == ARM_AM::rrx) in printSORegRegOperand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMInstPrinter.cpp | 52 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift() argument
54 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) in printRegImmShift()
58 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); in printRegImmShift()
59 O << getShiftOpcStr(ShOpc); in printRegImmShift()
61 if (ShOpc != ARM_AM::rrx) { in printRegImmShift()
391 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand() local
392 O << ", " << ARM_AM::getShiftOpcStr(ShOpc); in printSORegRegOperand()
393 if (ShOpc == ARM_AM::rrx) in printSORegRegOperand()
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| D | ARMMCCodeEmitter.cpp | 246 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
247 switch (ShOpc) { in getShiftOp()
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| /external/capstone/arch/ARM/ |
| D | ARMInstPrinter.c | 205 static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, unsigned ShImm) in printRegImmShift() argument
207 if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm)) in printRegImmShift()
212 SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); in printRegImmShift()
215 …at_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)ShOpc; in printRegImmShift()
217 …nsn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = (arm_shifter)ShOpc; in printRegImmShift()
220 if (ShOpc != ARM_AM_rrx) { in printRegImmShift()
949 ARM_AM_ShiftOpc ShOpc; in printSORegRegOperand() local
963 ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3)); in printSORegRegOperand()
965 SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); in printSORegRegOperand()
966 if (ShOpc == ARM_AM_rrx) in printSORegRegOperand()
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 205 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
206 switch (ShOpc) { in getShiftOp()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 175 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress() local
176 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); in convertToThreeAddress()
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| D | ARMISelDAGToDAG.cpp | 2371 SDValue ShOpc = in tryV6T2BitfieldExtractOp() local
2374 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc, in tryV6T2BitfieldExtractOp()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 197 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress() local
198 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); in convertToThreeAddress()
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| D | ARMISelDAGToDAG.cpp | 2866 SDValue ShOpc = in tryV6T2BitfieldExtractOp() local
2869 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc, in tryV6T2BitfieldExtractOp()
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| D | ARMISelLowering.cpp | 6143 unsigned ShOpc = N->getOpcode(); in Expand64BitShift() local
6159 if (ShOpc == ISD::SRL) { in Expand64BitShift()
6168 } else if (ShOpc == ISD::SRA) in Expand64BitShift()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 6014 unsigned ShOpc = IsLeft ? ISD::SHL : ISD::SRL; in expandROT() local
6020 Result = DAG.getNode(ISD::OR, DL, VT, DAG.getNode(ShOpc, DL, VT, Op0, And0), in expandROT()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 26821 unsigned ShOpc = ConstantAmt ? Opc : X86OpcV; in LowerShift() local
26822 SDValue R0 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt0)); in LowerShift()
26823 SDValue R1 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt1)); in LowerShift()
26824 SDValue R2 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt2)); in LowerShift()
26825 SDValue R3 = DAG.getNode(ShOpc, dl, VT, R, DAG.getBitcast(VT, Amt3)); in LowerShift()
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