| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 4482 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectRem() local
4483 if (!Src0Reg) in selectRem()
4494 unsigned QuotReg = fastEmitInst_rr(DivOpc, RC, Src0Reg, /*IsKill=*/false, in selectRem()
4500 Src1Reg, Src1IsKill, Src0Reg, in selectRem()
4546 unsigned Src0Reg = getRegForValue(Src0); in selectMul() local
4547 if (!Src0Reg) in selectMul()
4552 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
4560 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectMul() local
4561 if (!Src0Reg) in selectMul()
4570 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); in selectMul()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 4661 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectRem() local
4662 if (!Src0Reg) in selectRem()
4673 unsigned QuotReg = fastEmitInst_rr(DivOpc, RC, Src0Reg, /*IsKill=*/false, in selectRem()
4679 Src1Reg, Src1IsKill, Src0Reg, in selectRem()
4725 unsigned Src0Reg = getRegForValue(Src0); in selectMul() local
4726 if (!Src0Reg) in selectMul()
4731 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
4739 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectMul() local
4740 if (!Src0Reg) in selectMul()
4749 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); in selectMul()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 414 Register Src0Reg = I.getOperand(2).getReg(); in selectG_UADDO_USUBO_UADDE_USUBE() local
435 !RBI.constrainGenericRegister(Src0Reg, AMDGPU::SReg_32RegClass, *MRI) || in selectG_UADDO_USUBO_UADDE_USUBE()
589 Register Src0Reg = I.getOperand(1).getReg(); in selectG_INSERT() local
610 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI); in selectG_INSERT()
624 !RBI.constrainGenericRegister(Src0Reg, *Src0RC, *MRI) || in selectG_INSERT()
630 .addReg(Src0Reg) in selectG_INSERT()
652 Register Src0Reg = I.getOperand(2).getReg(); in selectG_INTRINSIC() local
657 for (Register Reg : { DstReg, Src0Reg, Src1Reg }) in selectG_INTRINSIC()
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| D | R600InstrInfo.h | 270 unsigned Src0Reg,
|
| D | R600InstrInfo.cpp | 1241 unsigned Src0Reg, in buildDefaultInstruction() argument
1254 .addReg(Src0Reg) // $src0 in buildDefaultInstruction()
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| D | AMDGPURegisterBankInfo.cpp | 2994 Register Src0Reg = MI.getOperand(2).getReg(); in getInstrMapping() local
2996 unsigned Src0Size = MRI.getType(Src0Reg).getSizeInBits(); in getInstrMapping()
3000 OpdsMapping[2] = AMDGPU::getValueMapping(getRegBankID(Src0Reg, MRI, *TRI), in getInstrMapping()
|
| D | SIInstrInfo.cpp | 4114 Register Src0Reg = Src0.getReg(); in legalizeOperandsVOP2() local
4126 Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill); in legalizeOperandsVOP2()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.h | 269 unsigned Src0Reg,
|
| D | R600InstrInfo.cpp | 1264 unsigned Src0Reg, in buildDefaultInstruction() argument
1277 .addReg(Src0Reg) // $src0 in buildDefaultInstruction()
|
| D | SIInstrInfo.cpp | 2108 unsigned Src0Reg = Src0.getReg(); in legalizeOperandsVOP2() local
2120 Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill); in legalizeOperandsVOP2()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1684 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectDivRem() local
1686 if (!Src0Reg || !Src1Reg) in selectDivRem()
1689 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1941 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectDivRem() local
1943 if (!Src0Reg || !Src1Reg) in selectDivRem()
1946 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 2595 Register Src0Reg = MI.getOperand(2).getReg(); in fewerElementsVectorCmp() local
2597 LLT SrcTy = MRI.getType(Src0Reg); in fewerElementsVectorCmp()
4199 Register Src0Reg = MI.getOperand(1).getReg(); in lowerShuffleVector() local
4201 LLT Src0Ty = MRI.getType(Src0Reg); in lowerShuffleVector()
4217 Val = Mask[0] == 0 ? Src0Reg : Src1Reg; in lowerShuffleVector()
4236 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg); in lowerShuffleVector()
4239 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; in lowerShuffleVector()
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