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Searched refs:V6 (Results 1 – 25 of 146) sorted by relevance

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/external/rust/crates/idna/tests/
D	IdnaTestV2.txt	285 a⒈com; ; [P1, V6]; xn--acom-0w1b; ; ; # a⒈com 287 A⒈COM; a⒈com; [P1, V6]; xn--acom-0w1b; ; ; # a⒈com 288 A⒈Com; a⒈com; [P1, V6]; xn--acom-0w1b; ; ; # a⒈com 289 xn--acom-0w1b; a⒈com; [V6]; xn--acom-0w1b; ; ; # a⒈com 290 xn--a-ecp.ru; a⒈.ru; [V6]; xn--a-ecp.ru; ; ; # a⒈.ru 292 xn--a.pt; €.pt; [V6]; xn--a.pt; ; ; # .pt 532 $; ; [P1, V6]; ; ; ; # $ 542 ⒕∝ٟ��．-��; ⒕∝ٟ��.-; [P1, V3, V6]; xn--7hb713lfwbi1311b.-; ; ; # ⒕∝ٟ.- 543 14.∝ٟ��.-��; 14.∝ٟ��.-; [P1, V3, V6]; 14.xn--7hb713l3v90n.-; ; ; # 14.∝ٟ.- 544 14.xn--7hb713l3v90n.-; 14.∝ٟ��.-; [V3, V6]; 14.xn--7hb713l3v90n.-; ; ; # 14.∝ٟ.- [all …]
/external/icu/android_icu4j/src/main/tests/android/icu/dev/data/unicode/
D	IdnaTestV2.txt	285 a⒈com; ; [P1, V6]; xn--acom-0w1b; ; ; # a⒈com 287 A⒈COM; a⒈com; [P1, V6]; xn--acom-0w1b; ; ; # a⒈com 288 A⒈Com; a⒈com; [P1, V6]; xn--acom-0w1b; ; ; # a⒈com 289 xn--acom-0w1b; a⒈com; [V6]; xn--acom-0w1b; ; ; # a⒈com 290 xn--a-ecp.ru; a⒈.ru; [V6]; xn--a-ecp.ru; ; ; # a⒈.ru 292 xn--a.pt; \u0080.pt; [V6]; xn--a.pt; ; ; # .pt 532 $; ; [P1, V6]; ; ; ; # $ 542 ⒕∝\u065F��．-��; ⒕∝\u065F��.-; [P1, V3, V6]; xn--7hb713lfwbi1311b.-; ; ; # ⒕∝ٟ.- 543 14.∝\u065F��.-��; 14.∝\u065F��.-; [P1, V3, V6]; 14.xn--7hb713l3v90n.-; ; ; # 14.∝ٟ.- 544 14.xn--7hb713l3v90n.-; 14.∝\u065F��.-; [V3, V6]; 14.xn--7hb713l3v90n.-; ; ; # 14.∝ٟ.- [all …]
/external/icu/icu4c/source/test/testdata/
D	IdnaTestV2.txt	285 a⒈com; ; [P1, V6]; xn--acom-0w1b; ; ; # a⒈com 287 A⒈COM; a⒈com; [P1, V6]; xn--acom-0w1b; ; ; # a⒈com 288 A⒈Com; a⒈com; [P1, V6]; xn--acom-0w1b; ; ; # a⒈com 289 xn--acom-0w1b; a⒈com; [V6]; xn--acom-0w1b; ; ; # a⒈com 290 xn--a-ecp.ru; a⒈.ru; [V6]; xn--a-ecp.ru; ; ; # a⒈.ru 292 xn--a.pt; \u0080.pt; [V6]; xn--a.pt; ; ; # .pt 532 $; ; [P1, V6]; ; ; ; # $ 542 ⒕∝\u065F��．-��; ⒕∝\u065F��.-; [P1, V3, V6]; xn--7hb713lfwbi1311b.-; ; ; # ⒕∝ٟ.- 543 14.∝\u065F��.-��; 14.∝\u065F��.-; [P1, V3, V6]; 14.xn--7hb713l3v90n.-; ; ; # 14.∝ٟ.- 544 14.xn--7hb713l3v90n.-; 14.∝\u065F��.-; [V3, V6]; 14.xn--7hb713l3v90n.-; ; ; # 14.∝ٟ.- [all …]
/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/data/unicode/
D	IdnaTestV2.txt	285 a⒈com; ; [P1, V6]; xn--acom-0w1b; ; ; # a⒈com 287 A⒈COM; a⒈com; [P1, V6]; xn--acom-0w1b; ; ; # a⒈com 288 A⒈Com; a⒈com; [P1, V6]; xn--acom-0w1b; ; ; # a⒈com 289 xn--acom-0w1b; a⒈com; [V6]; xn--acom-0w1b; ; ; # a⒈com 290 xn--a-ecp.ru; a⒈.ru; [V6]; xn--a-ecp.ru; ; ; # a⒈.ru 292 xn--a.pt; \u0080.pt; [V6]; xn--a.pt; ; ; # .pt 532 $; ; [P1, V6]; ; ; ; # $ 542 ⒕∝\u065F��．-��; ⒕∝\u065F��.-; [P1, V3, V6]; xn--7hb713lfwbi1311b.-; ; ; # ⒕∝ٟ.- 543 14.∝\u065F��.-��; 14.∝\u065F��.-; [P1, V3, V6]; 14.xn--7hb713l3v90n.-; ; ; # 14.∝ٟ.- 544 14.xn--7hb713l3v90n.-; 14.∝\u065F��.-; [V3, V6]; 14.xn--7hb713l3v90n.-; ; ; # 14.∝ٟ.- [all …]
/external/cronet/third_party/icu/source/test/testdata/
D	IdnaTestV2.txt	285 a⒈com; ; [P1, V6]; xn--acom-0w1b; ; ; # a⒈com 287 A⒈COM; a⒈com; [P1, V6]; xn--acom-0w1b; ; ; # a⒈com 288 A⒈Com; a⒈com; [P1, V6]; xn--acom-0w1b; ; ; # a⒈com 289 xn--acom-0w1b; a⒈com; [V6]; xn--acom-0w1b; ; ; # a⒈com 290 xn--a-ecp.ru; a⒈.ru; [V6]; xn--a-ecp.ru; ; ; # a⒈.ru 292 xn--a.pt; \u0080.pt; [V6]; xn--a.pt; ; ; # .pt 532 $; ; [P1, V6]; ; ; ; # $ 542 ⒕∝\u065F��．-��; ⒕∝\u065F��.-; [P1, V3, V6]; xn--7hb713lfwbi1311b.-; ; ; # ⒕∝ٟ.- 543 14.∝\u065F��.-��; 14.∝\u065F��.-; [P1, V3, V6]; 14.xn--7hb713l3v90n.-; ; ; # 14.∝ٟ.- 544 14.xn--7hb713l3v90n.-; 14.∝\u065F��.-; [V3, V6]; 14.xn--7hb713l3v90n.-; ; ; # 14.∝ٟ.- [all …]
/external/llvm/test/CodeGen/Hexagon/
D	eliminate-pred-spill.ll	51 %20 = tail call <1024 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %2, <32 x i32> %11) 52 …%21 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %20, <32 x i32> %11, <32 x i32> … 53 …%22 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %20, <32 x i32> %2, <32 x i32> %… 54 …%23 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %20, <32 x i32> undef, <32 x i32… 55 …%24 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %20, <32 x i32> %12, <32 x i32> … 56 %25 = tail call <1024 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %7, <32 x i32> %15) 57 …%26 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %25, <32 x i32> %15, <32 x i32> … 58 …%27 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %25, <32 x i32> %7, <32 x i32> %… 59 …%28 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %25, <32 x i32> %16, <32 x i32> … 60 …%29 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %25, <32 x i32> %8, <32 x i32> %… [all …]
D	v60-cur.ll	24 …%3 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %1, <16 x i32> %sline000.0114, i32 … 25 …%4 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> zeroinitializer, <16 x i32> %sline1… 26 …%5 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %2, <16 x i32> zeroinitializer, i32… 27 %6 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %3, <16 x i32> %sline000.0114) 28 %7 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %5, <16 x i32> zeroinitializer) 29 %8 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %6, i32 0, i32 0) 30 …%9 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %8, <32 x i32> zeroinitializer… 31 …%10 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %9, <32 x i32> undef, i32 und… 32 %11 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %10) 33 %12 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %11, <16 x i32> undef, i32 %shift) [all …]
D	vload-postinc-sel.ll	6 declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #0 7 declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #0 8 declare <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32>) #0 9 declare <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32>, <32 x i32>) #0 10 declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #0 11 declare <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32>, <64 x i32>) #0 12 declare <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32>, <32 x i32>) #0 31 %7 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> undef, <32 x i32> %6, i32 1) 32 %8 = tail call <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32> %7) #1 33 %9 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %8) #1 [all …]
D	v60Intrins.ll	379 %4 = call <512 x i1> @llvm.hexagon.V6.pred.and(<512 x i1> %1, <512 x i1> %3) 386 %10 = call <512 x i1> @llvm.hexagon.V6.pred.and.n(<512 x i1> %7, <512 x i1> %9) 391 %14 = call <512 x i1> @llvm.hexagon.V6.pred.not(<512 x i1> %13) 398 %20 = call <512 x i1> @llvm.hexagon.V6.pred.or(<512 x i1> %17, <512 x i1> %19) 405 %26 = call <512 x i1> @llvm.hexagon.V6.pred.or.n(<512 x i1> %23, <512 x i1> %25) 409 %29 = call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %28, i32 -1) 415 %34 = call <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1> %32, <16 x i32> %33, i32 -1) 420 %38 = call <512 x i1> @llvm.hexagon.V6.veqb(<16 x i32> %36, <16 x i32> %37) 425 %42 = call <512 x i1> @llvm.hexagon.V6.veqh(<16 x i32> %40, <16 x i32> %41) 430 %46 = call <512 x i1> @llvm.hexagon.V6.veqw(<16 x i32> %44, <16 x i32> %45) [all …]
D	vselect-pseudo.ll	14 …%0 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %.h63h32.2.us, <16 x i32> undef, i3… 15 …%1 = tail call <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1> undef, <16 x i32> undef, <16 x i32> %0) 16 %2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %1) 17 %3 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %2, i32 62) 18 %4 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %3) 26 declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1 27 declare <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1>, <16 x i32>, <16 x i32>) #1 28 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1 29 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1 30 declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #1
D	bitconvert-vector.ll	10 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #0 11 declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #0 12 declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0 17 %t1 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> %t0, <32 x i32> undef, i32 2) 18 …%t2 = tail call <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32> undef, <32 x i32> %t1, i32 -… 19 %t3 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %t2)
D	vec-pred-spill1.ll	32 %0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2) 33 %1 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %0, i32 16843009) 34 %2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 35 …%3 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1> %1, <16 x i32> %2, i32 -21474836… 40 %5 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1> %1, <16 x i32> %2, i32 -1) 45 %7 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1> %1, <16 x i32> %2, i32 0) 60 declare <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1>, <16 x i32>, i32) #2 63 declare <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #2 66 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #2
D	reg-scavengebug-3.ll	31 declare <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1>, i32) #1 37 declare <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1 40 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 46 declare <16 x i32> @llvm.hexagon.V6.vsubhnq(<512 x i1>, <16 x i32>, <16 x i32>) #1 63 %7 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 65 %8 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 66 %9 = call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %8, i32 16843009) 68 %10 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 69 %11 = call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %10, i32 16843009) 72 %14 = call <16 x i32> @llvm.hexagon.V6.vsubhnq(<512 x i1> %13, <16 x i32> undef, <16 x i32> undef)
/external/llvm/test/MC/ARM/
D	arm11-hint-instr.s	`2 @ RUN: FileCheck --check-prefix=CHECK-V6 %s < %t1 3 @ RUN: FileCheck --check-prefix=CHECK-ERROR-V6 %s < %t2 31 @ CHECK-V6: mov r0, r0 @ encoding: [0x00,0x00,0xa0,0xe1] 32 @ CHECK-ERROR-V6: error: instruction requires: armv6k 33 @ CHECK-ERROR-V6: yield 34 @ CHECK-ERROR-V6: ^ 35 @ CHECK-ERROR-V6: error: instruction requires: armv6k 36 @ CHECK-ERROR-V6: wfe 37 @ CHECK-ERROR-V6: ^ 38 @ CHECK-ERROR-V6: error: instruction requires: armv6k [all …]`
D	directive-arch_extension-mp.s	2 @ RUN: \| FileCheck %s -check-prefix CHECK-ARMv6 -check-prefix CHECK-V6 8 @ RUN: \| FileCheck %s -check-prefix CHECK-THUMBv6 -check-prefix CHECK-V6 17 @ CHECK-V6: error: architectural extension 'mp' is not allowed for the current base architecture 18 @ CHECK-V6-NEXT: .arch_extension mp 19 @ CHECK-V6-NEXT: ^ 24 @ CHECK-V6: error: instruction requires: mp-extensions armv7 28 @ CHECK-V6: error: architectural extension 'mp' is not allowed for the current base architecture 29 @ CHECK-V6-NEXT: .arch_extension nomp 30 @ CHECK-V6-NEXT: ^ 35 @ CHECK-V6: error: instruction requires: mp-extensions armv7
D	directive-arch_extension-sec.s	`2 @ RUN: \| FileCheck %s -check-prefix CHECK-V6 8 @ RUN: \| FileCheck %s -check-prefix CHECK-V6 15 @ CHECK-V6: error: architectural extension 'sec' is not allowed for the current base architecture 16 @ CHECK-V6-NEXT: .arch_extension sec 17 @ CHECK-V6-NEXT: ^ 23 @ CHECK-V6: error: instruction requires: TrustZone 26 @ CHECK-V6: error: architectural extension 'sec' is not allowed for the current base architecture 27 @ CHECK-V6-NEXT: .arch_extension nosec 28 @ CHECK-V6-NEXT: ^`
D	directive-arch_extension-idiv.s	`2 @ RUN: \| FileCheck %s -check-prefix CHECK-ARMv6 -check-prefix CHECK-V6 8 @ RUN: \| FileCheck %s -check-prefix CHECK-THUMBv6 -check-prefix CHECK-V6 17 @ CHECK-V6: error: architectural extension 'idiv' is not allowed for the current base architecture 18 @ CHECK-V6-NEXT: .arch_extension idiv 19 @ CHECK-V6-NEXT: ^ 34 @ CHECK-V6: error: architectural extension 'idiv' is not allowed for the current base architecture 35 @ CHECK-V6-NEXT: .arch_extension noidiv 36 @ CHECK-V6-NEXT: ^`
/external/llvm/test/CodeGen/Thumb/
D	ldr_ext.ll	`2 ; RUN: llc -mtriple=thumb-eabi -mattr=+v6 %s -o - \| FileCheck %s -check-prefix=V6 9 ; V6: ldrb 18 ; V6: ldrh 29 ; V6: ldrb 30 ; V6: sxtb 41 ; V6: ldrh 42 ; V6: sxth 52 ; V6: movs r0, #0 53 ; V6: ldrsh`
D	barrier.ll	`1 ; RUN: llc -mtriple=thumbv6-apple-darwin %s -o - \| FileCheck %s -check-prefix=V6 2 ; RUN: llc -mtriple=thumbv7-apple-darwin -mattr=-db %s -o - \| FileCheck %s -check-prefix=V6 6 ; V6-LABEL: t1: 7 ; V6: bl {{_*}}sync_synchronize`
/external/rust/crates/macaddr/src/
D	addr.rs	`8 V6(MacAddr6), enumerator 26 MacAddr::V6(_) => true, in is_v6() 44 MacAddr::V6(_) => false, in is_v8() 63 MacAddr::V6(addr) => addr.as_bytes(), in as_bytes() 71 MacAddr::V6(addr) in from() 91 MacAddr::V6(MacAddr6::from(bytes)) 104 MacAddr::V6(v6) => fmt::Display::fmt(v6, f), in fmt()`
/external/tcpdump/tests/
D	ospf6_print_lshdr-oobr.out	3 Options [V6, External, Router] 8 Options [V6, External, Router] 13 Options [V6, External, Router] 18 Options [V6, External, Router] 23 Options [V6, External, Router] 28 Options [V6, External, Router] 34 Options [V6, External, Router], DD Flags [Init, More, Master], MTU 1500, DD-Sequence 0x00001d46 37 Options [V6, External, Router], DD Flags [Init, More, Master], MTU 1500, DD-Sequence 0x0000242c 40 Options [V6, External, Router], DD Flags [More], MTU 1500, DD-Sequence 0x00001d46 [\|ospf3] 43 Options [V6, External, Router], DD Flags [More, Master], MTU 1500, DD-Sequence 0x00001d47 [\|ospf3] [all …]
D	ospf3_bc-vv.out	3 Options [V6, External, Router] 8 Options [V6, External, Router] 13 Options [V6, External, Router] 18 Options [V6, External, Router] 23 Options [V6, External, Router] 28 Options [V6, External, Router] 35 Options [V6, External, Router], DD Flags [Init, More, Master], MTU 1500, DD-Sequence 0x00001d46 38 Options [V6, External, Router], DD Flags [Init, More, Master], MTU 1500, DD-Sequence 0x0000242c 41 Options [V6, External, Router], DD Flags [More], MTU 1500, DD-Sequence 0x00001d46 58 Options [V6, External, Router], DD Flags [More, Master], MTU 1500, DD-Sequence 0x00001d47 [all …]
D	ospf3_ah-vv.out	`3 Options [V6, External, Router] 8 Options [V6, External, Router] 13 Options [V6, External, Router] 19 Options [V6, External, Router] 25 Options [V6, External, Router] 31 Options [V6, External, Router] 37 Options [V6, External, Router] 44 Options [V6, External, Router], DD Flags [Init, More, Master], MTU 1500, DD-Sequence 0x000012fd 47 Options [V6, External, Router] 53 Options [V6, External, Router], DD Flags [Init, More, Master], MTU 1500, DD-Sequence 0x000012fd [all …]`
/external/libxaac/decoder/armv8/
D	ixheaacd_overlap_add1.s	`71 UZP2 V6.8H, V3.8H, V3.8H 73 REV64 V6.8H, V6.8H 98 SMLAL V15.4S, V6.4H, V2.4H 128 UZP2 V6.8H, V3.8H, V3.8H 130 REV64 V6.8h, V6.8h 150 SMLAL V15.4S, V6.4H, V2.4H 157 LD1 {V6.4S}, [X10], X12 175 SQNEG V0.4S, V6.4S 183 UZP1 V7.8H, V6.8H, V6.8H 184 UZP2 V6.8H, V6.8H, V6.8H [all …]`
/external/llvm/test/CodeGen/ARM/
D	mulhi.ll	`1 ; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - \| FileCheck %s -check-prefix=V6 6 ; V6-LABEL: smulhi: 7 ; V6: smmul 23 ; V6-LABEL: umulhi: 24 ; V6: umull 41 ; V6-LABEL: t3: 42 ; V6: smmla`

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