1 /* 2 * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef VERSAL_DEF_H 8 #define VERSAL_DEF_H 9 10 #include <plat/arm/common/smccc_def.h> 11 #include <plat/common/common_def.h> 12 13 /* List all consoles */ 14 #define VERSAL_CONSOLE_ID_pl011 1 15 #define VERSAL_CONSOLE_ID_pl011_0 1 16 #define VERSAL_CONSOLE_ID_pl011_1 2 17 #define VERSAL_CONSOLE_ID_dcc 3 18 19 #define VERSAL_CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) 20 21 /* List all supported platforms */ 22 #define VERSAL_PLATFORM_ID_versal_virt 1 23 #define VERSAL_PLATFORM_ID_silicon 4 24 25 #define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM) 26 27 /* Firmware Image Package */ 28 #define VERSAL_PRIMARY_CPU 0 29 30 /******************************************************************************* 31 * memory map related constants 32 ******************************************************************************/ 33 #define DEVICE0_BASE 0xFF000000 34 #define DEVICE0_SIZE 0x00E00000 35 #define DEVICE1_BASE 0xF9000000 36 #define DEVICE1_SIZE 0x00800000 37 38 /* CRL */ 39 #define VERSAL_CRL 0xFF5E0000 40 #define VERSAL_CRL_TIMESTAMP_REF_CTRL (VERSAL_CRL + 0x14C) 41 #define VERSAL_CRL_RST_TIMESTAMP_OFFSET (VERSAL_CRL + 0x348) 42 43 #define VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 25) 44 45 /* IOU SCNTRS */ 46 #define VERSAL_IOU_SCNTRS 0xFF140000 47 #define VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG (VERSAL_IOU_SCNTRS + 0x0) 48 #define VERSAL_IOU_SCNTRS_BASE_FREQ (VERSAL_IOU_SCNTRS + 0x20) 49 50 #define VERSAL_IOU_SCNTRS_CONTROL_EN 1 51 52 /******************************************************************************* 53 * IRQ constants 54 ******************************************************************************/ 55 #define VERSAL_IRQ_SEC_PHY_TIMER 29 56 57 /******************************************************************************* 58 * CCI-400 related constants 59 ******************************************************************************/ 60 #define PLAT_ARM_CCI_BASE 0xFD000000 61 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 62 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 63 64 /******************************************************************************* 65 * UART related constants 66 ******************************************************************************/ 67 #define VERSAL_UART0_BASE 0xFF000000 68 #define VERSAL_UART1_BASE 0xFF010000 69 70 #if VERSAL_CONSOLE_IS(pl011) || VERSAL_CONSOLE_IS(dcc) 71 # define VERSAL_UART_BASE VERSAL_UART0_BASE 72 #elif VERSAL_CONSOLE_IS(pl011_1) 73 # define VERSAL_UART_BASE VERSAL_UART1_BASE 74 #else 75 # error "invalid VERSAL_CONSOLE" 76 #endif 77 78 #define PLAT_VERSAL_CRASH_UART_BASE VERSAL_UART_BASE 79 #define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ VERSAL_UART_CLOCK 80 #define VERSAL_CONSOLE_BAUDRATE VERSAL_UART_BAUDRATE 81 82 /******************************************************************************* 83 * Platform related constants 84 ******************************************************************************/ 85 #if VERSAL_PLATFORM_IS(versal_virt) 86 # define PLATFORM_NAME "Versal Virt" 87 # define VERSAL_UART_CLOCK 25000000 88 # define VERSAL_UART_BAUDRATE 115200 89 # define VERSAL_CPU_CLOCK 2720000 90 #elif VERSAL_PLATFORM_IS(silicon) 91 # define PLATFORM_NAME "Versal Silicon" 92 # define VERSAL_UART_CLOCK 100000000 93 # define VERSAL_UART_BAUDRATE 115200 94 # define VERSAL_CPU_CLOCK 100000000 95 #endif 96 97 /* Access control register defines */ 98 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 99 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 100 101 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 102 #define CRF_BASE 0xFD1A0000 103 #define CRF_SIZE 0x00600000 104 105 /* CRF registers and bitfields */ 106 #define CRF_RST_APU (CRF_BASE + 0X00000300) 107 108 #define CRF_RST_APU_ACPU_RESET (1 << 0) 109 #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) 110 111 #define FPD_MAINCCI_BASE 0xFD000000 112 #define FPD_MAINCCI_SIZE 0x00100000 113 114 /* APU registers and bitfields */ 115 #define FPD_APU_BASE 0xFD5C0000 116 #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20) 117 #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40) 118 #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44) 119 #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90) 120 121 #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8 122 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 123 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 124 125 /* PMC registers and bitfields */ 126 #define PMC_GLOBAL_BASE 0xF1110000 127 #define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40) 128 129 /* IPI registers and bitfields */ 130 #define IPI0_REG_BASE 0xFF330000 131 #define IPI0_TRIG_BIT (1 << 2) 132 #define PMC_IPI_TRIG_BIT (1 << 1) 133 #define IPI1_REG_BASE 0xFF340000 134 #define IPI1_TRIG_BIT (1 << 3) 135 #define IPI2_REG_BASE 0xFF350000 136 #define IPI2_TRIG_BIT (1 << 4) 137 #define IPI3_REG_BASE 0xFF360000 138 #define IPI3_TRIG_BIT (1 << 5) 139 #define IPI4_REG_BASE 0xFF370000 140 #define IPI4_TRIG_BIT (1 << 5) 141 #define IPI5_REG_BASE 0xFF380000 142 #define IPI5_TRIG_BIT (1 << 6) 143 144 #endif /* VERSAL_DEF_H */ 145